Integrated semiconductor memory with parallel test capability and redundancy method

A method for replacing memory cells (MC) with redundant memory cells (MCred) in a semiconductor memory including U block groups (GP.sub.u=1 . . . U) each having groups of M memory cells (MC) and word lines (WL), means for simultaneously testing several of the groups of M memory cells (MC) for operation in a test mode, each of the groups of memory cells being disposed along a respective word line (WL) within a respective one of the U block groups (GP.sub.u);

• the testing means being in the form of a parallel test device (PT) associated with the U block groups (GP.sub.u=1 . . . U) for writing in and evaluating data to be written into and read out of the semiconductor memory;
• the parallel test device including means for evaluating data read out in the test mode separately for each of the block groups;
• and I/O data lines (IO1, IO2, IO3) of the semiconductor memory separately carrying a result of the evaluation for each of the groups of M memory cells (MC), the semiconductor memory further including at least one redundant word line (WLred) having redundant memory cells (MCred), a redundant word line decoder (WLDECred) for selecting the at least one redundant word line (WLred) in the case of redundancy, and read amplifiers (SA) and bit switches (BSW) of replaced memory cells (MC) for connecting the redundant memory cells (MCred) to corresponding lines of the block databus (BKDB) in the case of redundancy, and a computer-controlled automatic testing and repair device having algorithms and means for replacing the memory cells (MC),
• which comprises testing all of the memory cells (MC) of the semiconductor memory in a test mode, identifying each defective memory cell group (MC) with each detected fault within the semiconductor memory through its address (ADR) applied from the outside and a respective I/O data line (IO1, IO2, IO3) on which the fault is detected, by means of the parallel test device (PT) and the automatic testing device, and supplying identification data being obtained for all defective memory cell groups to the automatic repair device which thereupon replaces the memory cell groups having defective memory cells (MC) by using the identification data.

A method for replacing memory cells (MC) with redundant memory cells (MCred) in a semiconductor memory including U block groups (GP.sub.u=1 . . . U) each having groups of M memory cells (MC) and word lines (WL), means for simultaneously testing several of the groups of M memory cells (MC) for operation in a test mode, each of the groups of memory cells being disposed along a respective word line (WL) within a respective one of the U block groups (GP.sub.u);

• the testing means being in the form of a parallel test device (PT) associated with the U block groups (GP.sub.u=1 . . . U) for writing in and evaluating data to be written into and read out of the semiconductor memory;
• the parallel test device including means for evaluating data read out in the test mode separately for each of the block groups;
• and I/O data lines (IO1, IO2, IO3) of the semiconductor memory separately carrying a result of the evaluation for each of the groups of M memory cells (MC), the semiconductor memory further including at least one group of M pairs of redundant bit lines (BLred) with redundant memory cells (MCred), M redundant read amplifiers (SAred), a redundant bit switch block (BKBSWred), a redundancy bit group decider (BITDECred) with an associated redundant bit group selection signal (BITSIGred) for selecting the at least one group in the case of redundancy, and the at least one group being connectible to corresponding lines of the block databus (BKDB), and a computer-controlled automatic testing and repair device having algorithms and means for replacing the memory cells (MC),
• which comprises testing all of the memory cells (MC) of the semiconductor memory in a test mode, identifying each defective memory cell group (MC) with each detected fault within the semiconductor memory through its address (ADR) applied from the outside and a respective I/O data line (IO1, IO2, IO3) on which the fault is detected, by means of a parallel test device (PT) and the automatic testing device, and supplying identification data being obtained for all defective memory cell groups to the automatic repair device which thereupon replaces the memory cell groups having defective memory cells (MC) by using the identification data.

A method for replacing memory cells (MC) with redundant memory cells (MCred) in a semiconductor memory including U block groups (GP.sub.u=1 . . . U) each having groups of M memory cells (MC) and word lines (WL), means for simultaneously testing several of the groups of M memory cells (MC) for operation in a test mode, each of the groups of memory cells being disposed along a respective word line (WL) within a respective one of the U block groups (GP.sub.u);

• the testing means being in the form of a parallel test device (PT) associated with the U block groups (GP.sub.u=1 . . . U) for writing in and evaluating data to be written into and read out of the semiconductor memory;
• the parallel test device including means for evaluating data read out in the test mode separately for each of the block groups;
• and I/O data lines (IO1, IO2, IO3) of the semiconductor memory separately carrying a result of the evaluation for each of the groups of M memory cells (MC), the semiconductor memory further including at least one redundant word line (WLred) having redundant memory cells (MCred), a redundant word line decoder (WLDECred) for selecting the at least one redundant word line (WLred) in the case of redundancy, and read amplifiers (SA) and bit switches (BSW) of replaced memory cells (MC) for connecting the redundant memory cells (MCred) to corresponding lines of the block databus (BKDB) in the case of redundancy, and a computer-controlled automatic testing and repair device having algorithms and means for replacing the memory cells (MC),
• which comprises testing all of the memory cells (MC) of the semiconductor memory in a test mode, identifying each defective memory cell (MC) with each detected fault within the semiconductor memory through its address (ADR) applied from the outside and a respective I/O data line (IO1, IO2, IO3) on which the fault is detected, by means of a parallel testing device (PT) and the automatic testing device, and supplying identification data being obtained for all defective memory cells (MC) to the automatic repair device which thereupon replaces the defective memory cells (MC) by using the identification data.

A method for replacing memory cells (MC) with redundant memory cells (MCred) in a semiconductor memory including U block groups (GP.sub.u=1 . . . U) each having groups of M memory cells (MC) and word lines (WL), means for simultaneously testing several of the groups of M memory cells (MC) for operation in a test mode, each of the groups of memory cells having disposed along a respective word line (WL) within a respective one of the U block groups (GP.sub.u);

• the testing means being in the form of a parallel test device (PT) associated with the U block groups (GP.sub.u=1 . . . U) for writing in and evaluating data to be written into and read out of the semiconductor memory;
• the parallel test device including means for evaluating data read out in the test mode separately for each of the block groups;
• and I/O data lines (IO1, IO2, IO3) of the semiconductor memory separately carrying a result of the evaluation for each of the groups of M memory cells (MC), the semiconductor memory further including at least one group of M pairs of redundant bit lines (BLred) with redundant memory cells (MCred), M redundant read amplifiers (SAred), a redundant bit switch block (BKBSWred), a redundancy bit group decoder (BITDECred) with an associated redundant bit group selection signal (BITSIGred) for selecting the at least one group in the case of redundancy, and the at least one group being connectible to corresponding lines of the block databus (BKDB), and a computer-controlled automatic testing and repair device having algorithms and means for replacing the memory cells (MC),
• which comprises testing all of the memory cells (MC) of the semiconductor memory in a test mode, identifying each defective memory cell (MC) with each detected fault within the semiconductor memory through its address (ADR) applied from the outside and a respective I/O data line (IO1, IO2, IO3) on which the fault is detected, by means of a parallel testing device (PT) and the automatic testing device, and supplying identification data being obtained for all defective memory cells (MC) to the automatic repair device which thereupon replaces the defective memory cells (MC) by using the identification data.