Microprocessor bus interface protocol analyzer

#1. Field of Use

#The present invention relates to data processing systems and, more particularly, to fault tolerant processors.

#2. Prior Art

#FIG. 1 is a block diagram of a multiprocessor system which incorporates the monitoring apparatus of the present invention.

#FIG. 2 shows in greater detail, a processing unit of FIG. 1 which incorporates the monitoring apparatus of the present invention.

#FIG. 3 shows in block diagram form, the monitoring apparatus of the present invention.

#FIG. 1 shows a multiprocessor system 10 which includes a plurality of central processing units 10-2 through 10-6 and peer processors 12-2 and 12-4 which tightly couple in common to a system bus 16 and to a main memory or system memory 14. Each processor, as shown, includes a bus interface area which enables the unit to transmit or receive requests in the form of commands, interrupts, data or responses/status to another unit on system bus 16. In the preferred embodiment, the system bus 16 operates asynchronously and uses a split bus cycle protocol which provides higher performance by granting other units bus cycles during the period of time a unit is waiting for main memory to furnish data in response to an earlier request made by that unit. For further information regarding this type of bus interface and operation, reference may be made to U.S. Pat. No. 3,997,896.

#Referring to FIG. 1, it is seen that each peer processor 12-2 and 12-4 includes a microprocessor 12-20, a local memory 12-30 and interface buses which couple to the bus interface circuits of block 12-40 a shown. The microprocessor 12-20 and local memory 12-30 are tightly coupled through a local processor bus 12-25. The microprocessor 12-20 is a high performance 32-bit processor which operates at clock speeds of up to 33 MHz and in the preferred embodiment corresponds to an Intel 80486 chip. The Intel 80486 chip includes a microprocessor, a floating point math coprocessor, a memory cache controller and an 8K RAM cache unit. The principal processing function is performed by the microprocessor while complex processing functions, such as floating operations, are performed by the math coprocessor. The internal cache unit provides fast access to the data required for processing. In the preferred embodiment, peer processors 12-2 and 12-4 operate under the control of a UNIX* operating system.

#In FIG. 1 the processors 10-2 through 10-6 function as host processors. In the preferred embodiment, each processor takes the form of a Bull DPS6000 system which operates under the control of the Bull HVS proprietary operating system. In the system of FIG. 1, each of the processors are organized to operate in an independent manner and have access to the full complement of system resources, such as input/output units, main memory and the like.