Byte tracking system and method
AssigneeAdvanced Micro Devices, Inc.
InventorHenry S.-F. Choy
Life of this patent
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Abstract
A byte tracking system (60) has a 32-bit wide system data bus (34). System bus interface unit (48) connects the system bus (34) to the transmit FIFO buffer memory (42) to supply 4-byte data words (62) to the FIFO buffer memory (42). The FIFO buffer memory (42) has word write and read accessibility. A 4:1 multiplexer (64) is connected at the output side of the FIFO buffer memory (42) by a 32-bit wide bus (66). The multiplexer (64) is used to multiplex correct bytes (63) from the data words (62) to an 8-bit output bus (68). A byte tracker circuit (70) controls the multiplexer (64) and determines which byte (63) is to be sent to the output bus (68). The bytes (63) supplied to output bus (68) are converted by a parallel to serial converter (69) to a serial bit stream, which is supplied to Manchester encoder/decoder (36).
Claims5
A system for transferring data in multiple byte words between a first bus and a second bus having different widths, which comprises a system interface connected to said first bus, a first-in-first-out buffer memory having an input connected to said system interface by a system interface bus having a width corresponding to said first bus, said first-in-first-out buffer memory being configured to store each multiple byte word in a multiple byte data field with an associated multiple bit byte validity field, said first-in-first-out buffer memory having an output connected by a buffer memory output bus having a width corresponding to said first bus, said buffer memory output bus being connected to a multiplexer, said multiplexer being connected to said second bus, and a byte tracker connected to the byte validity fields of said first-in-first-out buffer memory and to said multiplexer to control operation of said multiplexer to provide valid bytes from said first-in-first-out buffer memory to said second bus.
A method for transferring data in multiple byte words between a first bus and a second bus having different widths, which comprises storing the multiple byte words in a first-in-first-out buffer memory, storing associated multiple bit byte validity data for each of the multiple byte words in the first-in-first-out buffer memory, supplying the multiple byte words to a multiplexer, determining which bytes of the multiple byte words contain valid data using the multiple bit byte validity data, and supplying the valid bytes from the multiple byte words to the second bus from the multiplexer.
Dependencies are inferred from the claim text.