Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device having a page program mode of operation, comprising:

• a memory cell array comprised of a plurality of memory cells connected to a plurality of intersecting row lines and bit lines at the intersections thereof;
• a row decoder responsive to row address signals for selectively activating a selected one of said row lines;
• a data input buffer for receiving program data;
• a data line connected at one end thereof to said data input buffer;
• a plurality of column selecting MOS transistors each having a gate electrode, a first electrode connected to a respective one of said bit lines, and a second electrode connected to said data line;
• a column decoder having a plurality of outputs connected to said gate electrode of respective ones of said column selecting MOS transistors, said column decoder being responsive to column address signals for electrically connecting a selected one of said bit lines to said data line;
• a plurality of program voltage generating circuits each of which is selectively operable for generating a program voltage output having a first or second logic level, dependent upon the logic level of said program data;
• alternating pairs of said bit lines being commonly connected to said program voltage output of respective ones of said program voltage generating circuits;
• a plurality of first selecting MOS transistors having a first electrode connected to said program voltage output of respective ones of said program voltage generating circuits, a second electrode connected to respective ones of a first sequence of alternating ones of said bit lines, and a gate electrode;
• a plurality of second selecting MOS transistors having a first electrode connected to said program voltage output of said respective ones of said program voltage generating circuits, a second electrode connected to respective ones of a second sequence of alternating ones of said bit lines, and a gate electrode, said bit lines of said second sequence being interposed between said bit lines of said first sequence;
• and,
• a select circuit having a first output connected to said gate electrode of each of said first selecting MOS transistors and a second output connected to said gate electrode of each of said second selecting MOS transistors, said select circuit being selectively operable for selectively turning on either said first selecting MOS transistors or said second selecting MOS transistors, to thereby selectively couple either said bit lines of said first sequence or said bit lines of said second sequence to said program voltage output of said respective ones of said program voltage generating circuits.