Memory cell circuits, devices, systems and methods of operation

A memory cell, comprising:

• a storage element capable of being in a first or second state and having a node for presenting an electrical level representing said first state or second state;
• a first switching device having a first terminal connected to said node, wherein said first switching device is operable to close thereby connecting the state at the node to a second terminal of said first switching device;
• a first transistor having a gate, a first source/drain, and a second source/drain, said gate of said first transistor connected to said node;
• a second transistor having a gate, a first source/drain, and a second source/drain, said second transistor operable to switch as a function of the state at said node, said gate of said second transistor connected to receive a signal which is a function of an electrical level at said node, wherein said second transistor switches as a function of the electrical level at said node;
• and
• a single control switching device associated with said first and second transistors, wherein a control signal switches said control switching device such that the state at said node is determined by connecting to the first source/drains of said first and second transistors.

A memory cell, comprising:

• a node operable to present an electrical level representing a first state or a second state;
• a first switching device having first and second terminals and operable to switch as a function of the state at said node;
• a second switching device having first and second terminals and operable to switch as a function of the state at said node;
• and
• a first control switching device connected to said first switching device,
• a second control switching device connected to said second switching device, wherein a control signal switches said first and second control switching devices such that said state at said node is determined by connecting to the first terminals of said first and second switching devices.

A memory cell, comprising:

• a node operable to present an electrical level representing a first state or a second state;
• a port circuit having an output signal representative of the state at said node, said port circuit imposing a capacitance on said node;
• and
• a balancing circuit coupled to said node and imposing a capacitance on said node for balancing said output signal, said balancing circuit imposed capacitance being such that an equivalent capacitance is imposed on said node irrespective of said state at said node.

A method of determining the state at a node, comprising the steps of:

• activating a first and second switching device in response to the state at a node, each of said switching devices having a first and second terminal;
• activating a single control switching device associated with the first terminals of the first and second switching devices;
• and
• connecting to the second terminals of the first and second switching devices in order to determine the state at the node.

A system, comprising:

• a graphics processor;
• and
• a video memory coupled to said graphics processor, wherein said video memory comprises a plurality of memory cells, wherein each memory cell comprises:
• a node operable to present an electrical level representing a first state or a second state;
• a first switching device having a first terminal connected to said node, wherein said first switching device is operable to close thereby connecting the state at the node to a second terminal of said first switching device;
• a second switching device having first and second terminals and operable to switch as a function of the state at said node;
• a third switching device having first and second terminals and operable to switch as a function of the state at said node;
• and
• a single control switching device associated with said second and third switching devices, wherein a control signal switches said control switching device such that the state at said node is determined by connecting to the first terminals of said second and third switching devices.

A system comprising:

• a graphics processor;
• and
• a video memory coupled to said graphics processor, wherein said video memory comprises a plurality of memory cells, wherein each memory cell comprises:
• a storage element capable of being in a first or second state and having a node for presenting an electrical level representing said first state or second state;
• a first switching device having a first terminal connected to said node, wherein said first switching device is operable to close thereby connecting the state at the node to a second terminal of said first switching device;
• a first transistor having a gate, a first source/drain, and a second source/drain, said gate of said first transistor connected to said node;
• a second transistor having a gate, a first source/drain, and a second source/drain, said second transistor operable to switch as a function of the state at said node, said gate of said second transistor connected to receive a signal which is a function of an electrical level at said node, wherein said second transistor switches as a function of the electrical level at said node;
• and
• a single control switching device associated with said first and second transistors, wherein a control signal switches said control switching device such that the state at said node is determined by connecting to the first source/drains of said first and second transistors.

A system, comprising:

• a graphics processor;
• and
• a video memory coupled to said graphics processor, wherein said video memory comprises a plurality of memory cells, wherein each memory cell comprises:
• a node operable to present an electrical level representing a first state or a second state;
• a port circuit having an output signal representative of the state at said node, said port circuit imposing a capacitance on said node;
• and
• a balancing circuit coupled to said node and imposing a capacitance on said node for balancing said output signal, such that an equivalent capacitance is imposed on said node irrespective of said state at said node.