Random access memory device with columns of redundant memory cells distributed to memory cell arrays and shared therebetween

A random access memory device comprising:

• a) a plurality of regular memory cell blocks respectively assigned block addresses, and each having columns of regular memory cells respectively assigned column addresses;
• b) at least one column of redundant memory cells associated with one of said plurality of regular memory cell blocks, said redundant memory cells respectively storing data bits, one of said columns of regular memory cells of any one of said plurality of regular memory cell blocks being replaced with said at least one column of redundant memory cells when said one of said columns contains at least one defective regular memory cell;
• c) a plurality of row address decoder circuits respectively associated with said one of said plurality of regular memory cell blocks and with the others of said plurality of regular memory cell blocks, and selectively enabled with block selecting signals indicative of one of said block addresses;
• d) a plurality of column selector circuits respectively associated with said plurality of regular memory cell blocks, and each responsive to column selecting signals indicative of one of said column addresses for selecting a column of regular memory cells from the associated regular memory cell block;
• e) at least one transfer means coupled with said at least one column of redundant memory cells, and responsive to a redundant column selecting signal for transferring one of said data bits stored in said redundant memory cells;
• f) a plurality of amplifier means respectively coupled with said plurality of column selector circuits for a read-out mode and a write-in mode of operation, one of said plurality of amplifier means being further coupled with said transfer means, said plurality of amplifier means being selectively enabled with said block selecting signals;
• g) a program circuit storing a set of block and column addresses assigned to said one of said columns of regular memory cells containing said at least one defective regular memory cell, and comparing block and column addresses indicated by external address bits to see whether or not said block and column addresses are consistent with said set of block and column addresses, said program circuit producing a disable signal and said redundant column selecting signal when said block and column addresses are consistent with said set of block and column addresses;
• h) a column address decoder circuit selectively shifting said column selecting signals to an active level on the basis of parts of said external address bits indicative of said one of said column addresses in the absence of said disable signal;
• and
• i) a block address decoder circuit selectively shifting said block selecting signals to an active level on the basis of others of said external address bits indicative of said one of said block addresses in the absence of said disable signal, said block address decoder circuit being responsive to said redundant column selecting signal in the presence of said disable signal for shifting one of said block selecting signals indicative of said one of said plurality of regular memory cell blocks associated with said at least one column of redundant memory cells to said active level.