Semiconductor memory device having read/write operation improved in pipe line processing

A semiconductor memory device having a plurality of memory cells arranged in a matrix manner of rows and columns, for writing information into a memory cell corresponding to a specified row and column, and for reading out information held in the corresponding memory cell, comprising:

• a row address buffer for inputting a row address,
• a row decoder for specifying said input row address,
• a column address buffer for inputting sequentially column address with respect to said input row address,
• a first column address latch for holding one of said input column address,
• a first column decoder for specifying a column address held by said first column address holding means,
• a second column address latch for holding a column address input succeeding said column address held by said first column address latch,
• a second column decoder for specifying a column address held by said second column address latch,
• a write driver for writing information to a memory cell corresponding to specified row and column addresses,
• a preamplifier for reading out information with respect to a memory cell corresponding to specified row and column addresses, and
• a controller for operating said write driver or preamplifier according to first row and column addresses specified by said row decoder and said first column decoder, for enabling said second column address latch before the termination of the operation according to said first row and column addresses, and for operating said write driver or preamplifier according to second row and column addresses specified by said row decoder and second column decoder after the termination of the operation according to said first row and column addresses.

A method of controlling information reading operation in a semiconductor memory device including operation cycles based on a plurality of consecutive memory cycle times, said method comprising the steps of:

• i) at a first operation cycle
• latching an input column address, and
• operating a first column decoder and a first preamplifier according to said latched column address,
• ii) at a second operation cycle
• latching a column address input for the next reading operation,
• operating a second column decoder and a second preamplifier according to said latched column address, and holding in an output latch a data read out by the preceding operation cycle, and
• providing said held data via an output buffer.

A method of controlling information read/write operation in a semiconductor memory device operated in one of read, modify, and write cycles, comprising the steps of:

• i) at a first operation cycle
• latching an input first column address,
• operating a first column decoder and a preamplifier according to said latched first column address,
• ii) at a second operation cycle
• latching a second column address input for a succeeding reading,
• holding a first data read out by the preceding operation cycle in an output latch,
• providing said held first data via an output buffer,
• iii) at a third operation cycle
• latching a second data for writing to write said latched data by the operation of a write driver circuit,
• iv) at a fourth operation cycle
• operating a second column decoder according to a second column address for reading which is latched by said second operation cycle,
• holding in an output latch a third data read out,
• providing said held data via an output buffer.

A method of operating a semiconductor memory device having a plurality of memory cells arranged in a matrix of rows and columns for writing information into a memory cell corresponding to a specified row and column and for reading out information held in a corresponding memory cell, said method comprising the steps of:

• inputting a row address,
• specifying said input row address,
• inputting a column address with respect to said input row address,
• holding an input column address,
• specifying a held column address,
• carrying out reading operation of information with respect to a memory cell corresponding to first row and column addresses specified by a row address specify means and a first column address specify means,
• holding separately a column address input succeeding said held column address holding said read out information, and
• specifying said separately held column address, and
• carrying out information reading operation with respect to a memory cell corresponding to said specified column and said preceding held column address, and providing said held information.