US 5,293,345 AGranted

Semiconductor memory device having a data detection circuit with two reference potentials

AssigneeKabushiki Kaisha Toshiba

InventorHiroshi Iwahashi

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Abstract

A semiconductor memory device comprises a memory cell for storing a binary data, a first reference cell storing a first logic level of a binary data, a second reference cell storing a second logic level of a binary data, a first load circuit connected to the memory cell, a second load circuit connected to the first reference cell, a third load circuit connected to the second reference cell, and a data detection circuit for detecting the stored data of the memory cell by comparing an output from the first load circuit with the outputs from the second and third load circuits.

Claims18

Dependent claims

A semiconductor memory device comprising:

a memory cell for storing binary data, said cell being connected to a signal line to which a first load circuit is connected;
a first reference cell storing a first logic level of binary data, said first reference cell being connected to a first reference line, a second load circuit having an identical current supply ability as that of said first load circuit and a first capacitor, for compensating parasitic capacitance of the signal line, both said second load circuit and said first capacitor being connected to said first reference line, wherein, since the second load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, a fluctuation in a power supply voltage has the same effect for both said memory cell and the first reference cell, thereby preventing an erroneous operation of the semiconductor memory device;
a second reference cell storing a second logic level of binary data, said second reference cell being connected to a second reference line, a third load circuit having an identical current supply ability as that of said first load circuit and a second capacitor, for compensating parasitic capacitance of the signal line, both said third load circuit and said second capacitor being connected to said second reference line, wherein, since the third load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, the fluctuation in the power supply voltage has the same effect for both said memory cell and the second reference cell, thereby preventing an erroneous operation of the semiconductor memory device;
and
a data detection circuit for detecting the stored data of said memory cell, said data detection circuit having a first input, a second input, a third input and an output, said first input being connected to said signal line, said second input being connected to said first reference line, said third input being connected to said second reference line, said data detection circuit comparing a potential of said signal line with potentials of said first and second reference lines, a logic level of the output being determined by comparing the potential of said signal line with the potentials of said first and second reference lines.

2 more elements

A semiconductor memory device comprising:

a memory cell for storing binary data, said memory cell having a floating gate, said memory cell being connected to a signal line to which a first load circuit is connected, a logic state of the binary data stored in said memory cell being determined by whether or not electrons have been injected into said floating gate;
a first reference cell storing a first logic level of binary data, said first reference cell being connected to a first reference line, a second load circuit having an identical current supply ability as that of said first load circuit and a first capacitor, for compensating parasitic capacitance of the signal line, both said second load circuit and said first capacitor being connected to said first reference line, said first logic level corresponding to said stored data of said memory cell when electrons are not injected in said floating gate, wherein, since the second load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, a fluctuation in a power supply voltage has the same effect for both said memory cell and the first reference cell, thereby preventing an erroneous operation of the semiconductor memory device;
a second reference cell storing a second logic level of binary data, said second reference cell being connected to a second reference line, a third load circuit having an identical current supply ability to said first load circuit and a second capacitor, for compensating parasitic capacitance present on the signal line, both said third load circuit and said second capacitor being connected to said second reference cell, said second logic level corresponding to said stored data of said memory cell when electrons are injected in said floating gate, wherein, since the third load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, the fluctuation in the power supply voltage has the same effect for both said memory cell and the second reference cell, thereby preventing an erroneous operation of the semiconductor memory device;
and
a data detection circuit for detecting the stored data of said memory cell, said data detection circuit having a first input, a second input, a third input and an output, said first input being connected to said signal line, said second input being connected to said first reference line, said third input being connected to said second reference line, said data detection circuit comparing a potential of said signal line with potentials of said first and second reference lines, a logic level of the output being determined by comparing the potential of said signal line with the potentials of said first and second reference lines.

2 more elements

A semiconductor memory device comprising:

a memory array having a plurality of memory cells arranged in a matrix form with column lines and row lines, each of said memory cells storing binary data;
a column decoder to select one of said column lines to which a first load circuit is connected;
a row decoder to select one of said row lines;
a first reference column line connecting a plurality of first reference cells, each of said first reference cells storing a first logic level of binary data, said first reference column line to which a second load circuit having an identical current supply ability as that of said first load circuit, and a first capacitor for compensating parasitic capacitance of the column line are connected, wherein, since the second load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, a fluctuation in a power supply voltage has the same effect for both said memory cell and the first reference cell, thereby preventing an erroneous operation of the semiconductor memory device;
a second reference column line connecting a plurality of second reference cells, each of said second reference cells storing a second logic level of binary data, said second reference column line to which a third load circuit having an identical current supply ability as that of said first load circuit, and a second capacitor for compensating parasitic capacitance of the column line are connected, wherein, since the third load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, the fluctuation in the power supply voltage has the same effect for both said memory cell and the second reference cell, thereby preventing an erroneous operation of the semiconductor memory device;
and
a data detection circuit for detecting the stored data of said memory cells, said data detection circuit having a first input, a second input, a third input and an output, said first input being connected to selected one of said column lines, said second input being connected to said reference column line, said third input being connected to said second reference column line, said data detection circuit comparing a potential of said selected column line with potentials of said first and second reference column lines, a logic level of the output being determined by comparing the potential of said selected column line with the potentials of said first and second reference column lines.

4 more elements

Dependencies are inferred from the claim text.

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Abstract

A semiconductor memory device comprising:

a memory cell for storing binary data, said cell being connected to a signal line to which a first load circuit is connected;
a first reference cell storing a first logic level of binary data, said first reference cell being connected to a first reference line, a second load circuit having an identical current supply ability as that of said first load circuit and a first capacitor, for compensating parasitic capacitance of the signal line, both said second load circuit and said first capacitor being connected to said first reference line, wherein, since the second load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, a fluctuation in a power supply voltage has the same effect for both said memory cell and the first reference cell, thereby preventing an erroneous operation of the semiconductor memory device;
a second reference cell storing a second logic level of binary data, said second reference cell being connected to a second reference line, a third load circuit having an identical current supply ability as that of said first load circuit and a second capacitor, for compensating parasitic capacitance of the signal line, both said third load circuit and said second capacitor being connected to said second reference line, wherein, since the third load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, the fluctuation in the power supply voltage has the same effect for both said memory cell and the second reference cell, thereby preventing an erroneous operation of the semiconductor memory device;
and
a data detection circuit for detecting the stored data of said memory cell, said data detection circuit having a first input, a second input, a third input and an output, said first input being connected to said signal line, said second input being connected to said first reference line, said third input being connected to said second reference line, said data detection circuit comparing a potential of said signal line with potentials of said first and second reference lines, a logic level of the output being determined by comparing the potential of said signal line with the potentials of said first and second reference lines.

2 more elements