Dynamic semiconductor memory having a read amplifier drive circuit for achieving short access times with a low total peak current
AssigneeSiemens Aktiengesellschaft
InventorsWolfgang Raab, Heribert Geib
Life of this patent
Estimating the term…
Abstract
The dynamic semiconductor memory is divided into word line blocks and bit line blocks, word line blocks consisting of a plurality of bit line blocks, which includes for each bit line block a local SAN driver (LTN) and an decelerator circuit for driving the read amplifiers (LV1 . . . LVi) associated with the respective bit line block, and the accelerator circuits of which can be driven in such a way that, to achieve a low total peak current, only the accelerator circuit belonging to the bit line block is active whose bit lines are switched through to IO lines (IO, ION). The accelerator circuit consists, for example, of only one driver transistor (NT.sub.n+1) in each case.
Claims12
A dynamic semiconductor memory, comprising:
- a memory cell arrangement which has at least one word line block, said at least one word line block being composed of a multiplicity of bit line blocks, each of the bit line blocks having a multiplicity of bit line pairs;
- a multiplicity of read amplifier blocks, each of the read amplifier blocks having a multiplicity of read amplifiers, each of the read amplifiers being connected to a bit line pair of a bit line block which is allocated to a respective read amplifier block and being constructed from an n-channel part and a p-channel part;
- read amplifiers having amplified read signals that are switchable through to IO lines as a function of bit-line selection signals, the bit-line selection signals being produced by means of a column decoder;
- a multiplicity of local drivers, a respective local driver being provided for common drive of n-channel parts of read amplifiers of a respective read amplifier block;
- each of the local drivers, in order to achieve accelerated evaluation with a low peak current, additionally having an acceleration circuit with a driver transistor and being connected to a first terminal of the driver transistor;
- and
- each of the acceleration circuits that are drivable such that the accelerated evaluation takes place only in a read amplifier block in which amplified read signals are also switched through to the IO lines as a function of the bit-line selection signals.
Dependencies are inferred from the claim text.