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AssigneeSharp Kabushiki Kaisha
InventorMakoto Ihara
Estimating the term…
A peripheral circuit in a dynamic semiconductor memory device has a data line bias circuit and a timing generator circuit. The data line bias circuit has a switch connected between data lines and an internal voltage drop potential line having an intermediate potential between a power supply potential and a ground potential. When the switch is turned on, the data line bias circuit forms a current path connecting the internal voltage drop potential line and the data lines, and this current path is separated from ground. Therefore, electric current does not flow wastefully to ground. The timing generator circuit generates a control signal for activating pull-down transistors in a sense amplifier, a control signal for activating a column address decoder, and a control signal for activating pull-up transistors in the sense amplifier in that order, so that amplification of the signal on the bit lines, transfer of the amplified signal from the bit lines to the data lines, and bit line restoring are performed in that order.
A peripheral circuit in a dynamic semiconductor memory device comprising:
A peripheral circuit in a dynamic semiconductor memory device comprising:
A peripheral circuit in a dynamic semiconductor memory device comprising:
A method of operating a peripheral circuit in a dynamic semiconductor memory device comprising a plurality of sense amplifiers each of which includes a pair of pull-up transistors and a pair of pull-down transistors and is connected to complementary bit lines for sense-amplifying a potential difference between the complementary bit lines, a main amplifier connected to complementary data lines for further amplifying the potential difference amplified by the sense amplifiers, and a plurality of column address decoders for controlling transfer gates provided between each sense amplifier and the complementary data lines, comprising the steps of:
Dependencies are inferred from the claim text.