Pattern layout of power source lines in semiconductor memory device

A semiconductor memory device comprising:

• a semiconductor body;
• a memory area provided in said semiconductor body;
• a first power source line arranged around said memory area and applied with a first potential;
• a second power source line arranged in the surrounding region of said first power source line and applied with a second potential;
• a first circuit disposed in that area of said semiconductor body which lies between said first and second power source lines and driven by a potential difference between said first and second potentials;
• a third power source line arranged in the surrounding region of said second power source line and applied with a third potential;
• and
• a second circuit disposed in that area of said semiconductor body which lies between said second and third power source lines and driven by a potential difference between said second and third potentials, wherein the third potential is supplied from the exterior, the second potential is a ground potential supplied form the exterior, and the first potential is a lowered potential difference between the third potential and the ground potential.

A semiconductor memory device comprising:

• a semiconductor body;
• a first memory area provided in said semiconductor body;
• a second memory area provided in said semiconductor body and spaced from said first memory area;
• a first power source line comprising a first portion surrounding both said first and second memory areas and a second portion located in the space between said first and second memory areas, said first power source line applied with a first potential;
• a second power source line comprising a first portion surrounding said first portion of said first power source line and a second portion located in the space between said first and second memory areas, said second power source line applied with a second potential;
• a first circuit disposed in that area of said semiconductor body which lies between said second portion of said first power source line and said second portion of said second power source line, said first circuit driven by a potential difference between said first and second potentials;
• a third power source line arranged in the surrounding region of said second power source line and applied with a third potential;
• a second circuit disposed in that area of said semiconductor body which lies between said first portion of said second power source line and said third power source line and driven by a potential difference between said second and third potentials;
• and
• lowering means for lowering the potential difference between said second and third potentials to produce the first potential.

A semiconductor memory device comprising:

• a semiconductor body;
• a first memory area provided in said semiconductor body;
• a second memory area provided in said semiconductor body and spaced form said first memory area;
• a first power source line comprising a first portion surrounding both said first and second memory areas and a second portion located in the space between said first and second memory areas, and first power source line applied with a first potential;
• a second power source line comprising a first portion surrounding said first portion of said first power source line and a second portion located in the space between said first and second memory areas, said second power source line applied with a second potential and being formed of a layer at a level different from that of a layer forming said first power source line;
• a first circuit disposed in that area of said semiconductor body which lies between said second portion of said first power source line and said second portion of said second power source line, said first circuit driven by a potential difference between said first and second potentials;
• a third power source line arranged in the surrounding region of said second power source line and applied with a third potential;
• and
• a second circuit disposed in that area of said semiconductor body which lies between said first portion of said second power source line and said third power source line and driven by a potential difference between said second and third potentials,
• wherein said second power source line is formed of a first-level layer containing aluminum and said first power source line if formed of a second-level layer containing aluminum.

A semiconductor memory device comprising:

• a semiconductor body;
• a first memory area provided in said semiconductor body;
• a second memory area provided in said semiconductor body in a position separated from said first memory area;
• a first power source line comprising a portion surrounding said first and second memory areas and at least another portion located between said first and second memory areas and applied with a first potential;
• a second power source line comprising a portion surrounding said first power source line and at least another portion located between said first and second memory areas, and applied with a second potential, said second power source line being formed of a layer at a level different from that of a layer forming said first power source;
• a first circuit disposed in that area of said semiconductor body which lies between said at least another portion of said first power source line and said at least another portion of said second power source line, and driven by a potential difference between said first and second potentials;
• a third power source line arranged in the surrounding region of said second power source line and applied with a third potential;
• and
• a second circuit disposed in that area of said semiconductor body which lies between said second and third power source lines and driven by a potential difference between said second and third potentials, wherein the third potential is supplied from the exterior, the second potential is a ground potential supplied form the exterior, and the first potential is a lowered potential difference between the third potential and the ground potential.