Method of logic circuit simulation

A method of simulating delay time in a logic circuit, comprising the steps of:

• reading delay time of the logic element itself calculated in advance;
• converting an output logic value of said logic element to a voltage value;
• forming a circuit equation based on connection information of an output impedance circuit of said logic element;
• calculating a voltage value at an arbitrary node of said output impedance circuit by solving said circuit equation;
• and
• converting a voltage value of an input node of a logic element in the succeeding stage to a logic value;
• whereby
• delay time between an input node of an arbitrary logic element and an input node of an arbitrary logic element of the succeeding stage can be accurately simulated.