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US 5,293,212 AGranted
Non-volatile semiconductor memory device allowing erase of storage data of an arbitrary memory cell and method of erasing data in non-volatile semiconductor memory device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsMakoto Yamamoto, Kazuo Kobayashi
Life of this patent
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Abstract
A flash EEPROM with each memory cell including a single transistor, structured, to erase only the data of a desired memory cell, such that a high voltage of 10V is applied to one of all the bit lines in each block, a ground potential of 0V is applied to one of all the word lines in a memory array and a positive potential is applied to the other word lines in a data erasing to cause a tunnel phenomenon between a floating gate and a drain of one memory cell in each of blocks constituting the memory array.
Claims13
A non-volatile semiconductor memory device comprising:
- memory cells arranged in a plurality of rows and columns,
- a plurality of word lines provided corresponding to said plurality of rows,
- a plurality of bit lines provided corresponding to said plurality of columns,
- each of said plurality of memory cells including a field effect semiconductor device having a first conduction terminal connected to a corresponding one of said bit lines, a control terminal connected to a corresponding one of said word lines, a floating gate region for storing electric charges and a second conduction terminal,
- first selecting means for selecting one of said plurality of bit lines in response to an address signal in a selective erasing mode of operation of said memory device, and
- second selecting means for selecting one of said plurality of word lines in response to said address signal in said selective erasing mode of operation of said memory device, and
- first voltage supplying means for supplying a voltage across said one bit line selected by said first selecting means and said one word line selected by said second selecting means whereby a charge stored on the floating gate of a corresponding floating gate region is removed therefrom by a tunnel phenomenon caused between the corresponding first conduction terminal and the corresponding floating gate region.
4 more elements
A non-volatile semiconductor memory device having a selective erasing mode and a total erasing mode, comprising;
- a plurality of memory cells arranged in a plurality of rows and columns,
- a plurality of word lines provided corresponding to said plurality of rows,
- a plurality of bit lines provided corresponding to said plurality of columns,
- each of said plurality of memory cells including a field effect semiconductor device having a first conduction terminal connected to a corresponding bit line, a control terminal connected to a corresponding word line, a floating gate region for storing electrical charges and a second conduction terminal,
- said second conduction terminals of said plurality of said plurality of memory cells in rows and columns being connected together,
- first selecting means being activated in said selective erasing mode to select one of said plurality of bit lines to apply a predetermined high potential to the first conduction terminal of said plurality of memory cells connected to the selected bit line and said first selecting means being inactivated in said total erasing mode,
- second selecting means being activated in said selective erasing mode to select one of said plurality of word lines to apply a predetermined low potential to the control terminals of said plurality of memory cells connected to the selective word line and said second selecting means being inactivated in said total erasing mode, and
- total erasing means being inactivated in said total erasing mode to apply said predetermined high potential to said second conduction terminals connected together and said erasing means being inactivated in said selective erasing mode.
5 more elements
A non-volatile semiconductor memory device comprising:
- memory cells arranged in a plurality of rows and columns,
- a plurality of word lines provided corresponding to said plurality of rows,
- a plurality of bit lines provided corresponding to said plurality of columns,
- each of said plurality of memory cells including a field effect semiconductor device having a first conduction terminal connected to a corresponding one of said bit lines, a control terminal connected to a corresponding one of said word lines, a floating gate region for storing electric charges and a second conduction terminal, first, second and third voltages respectively applied to said first and second conduction terminals and said control terminal predetermined to store a charge on said floating gate region respective application of a fourth voltage, a fifth voltage and said second voltages to said first and second conduction terminals and said control terminal predetermined to remove a charge from said floating gate region through said first conduction terminal;
- first selecting means responsive to an address signal for selectively supplying said first voltage to one of said plurality of bit lines in a write mode of operation and selectively supplying said fourth voltage to one of said plurality of bit lines in a selective erasing mode of operation,
- second selecting means responsive to said address signal for selectively supplying said third voltage to one of said plurality of word lines in said write mode of operation and selectively supplying said second and fifth voltages to said plurality of word lines in said selective erasing mode of operation, and
- a source voltage circuit for respectively supplying said second and fifth voltages to said second conduction terminals in said write and selective erasing modes of operation,
- said second voltage being less than said first and fifth voltages and said third and fourth voltages each being greater than said second voltage.
5 more elements
A non-volatile semiconductor memory device comprising:
- a plurality of memory cells arranged in a matrix of rows and columns, each having a source electrode, a drain electrode, a floating gate electrode and a control electrode;
- a plurality of word lines arranged in rows, each word line connected to said control electrodes of said plurality of memory cells arranged in the corresponding row;
- a plurality of bit lines arranged in columns, each bit line connected to said drain electrodes of said plurality of memory cells arranged in the corresponding columns;
- a source electrode line connected to said source electrodes of said plurality of memory cells;
- a word line voltage applying means for applying a first voltage to a selected word line and for applying a second voltage, which is higher than said first voltage to non-selected word lines in an erase mode;
- a bit line voltage applying means for applying a third voltage, which is higher than said second voltage, to a selected bit line and for applying a fourth voltage, which is lower than said third voltage, to non-selected bit lines or maintaining said non-selected bit lines in an electrically floating gate in said erase mode;
- and
- a source electrode line voltage applying means for applying a fifth voltage, which is lower than said third voltage, to said source electrode line or for maintaining said source electrode line in an electrically floating state in said erase mode.
5 more elements
A non-volatile semiconductor memory device comprising:
- a plurality of memory cells arranged in a matrix of rows and columns, each having a source electrode, a drain electrode, a floating gate electrode and a control electrode, said memory cell array divided into a plurality of memory cell groups in a direction of columns;
- a plurality of word lines arranged in rows, each word line connected to said control electrodes of said plurality of memory cells arranged in the corresponding row;
- a plurality of bit lines arranged in columns, each bit line connected to said drain electrodes of said plurality of memory cells arranged in the corresponding columns;
- a source electrode line connected to said source electrodes of said plurality of memory cells;
- a word line voltage applying means for applying a first voltage to a selected word line and for applying a second voltage, which is higher than said first voltage to non-selected word lines in an erase mode;
- a bit line voltage applying means having a plurality of bit line voltage applying blocks, each block provided in the corresponding memory cell group and for applying a third voltage, which is higher than said second voltage, to a selected bit line and for applying a fourth voltage, which is lower than said third voltage, to non-selected bit lines or maintaining said non-selected bit lines in an electrically floating state in said erase mode;
- and
- a source electrode line voltage applying means for applying a fifth voltage, which is lower than said third voltage to said source electrode line or for maintaining said source electrode line in an electrically floating state in said erase mode.
5 more elements
A method of erasing data of a non-volatile semiconductor memory device comprising memory cells arranged in a plurality of rows and columns, a plurality of word lines provided corresponding to said plurality of rows, and a plurality of bit lines provided corresponding to said plurality of columns, each of said plurality of memory cells including a field effect semiconductor device having a first conduction terminal connected to a corresponding bit line, a control terminal connected to a corresponding one of the word line, a floating gate region for storing electric charges and a second conduction terminal, the method comprising the steps of:
- selecting one of said plurality of bit lines in response to an address signal,
- selecting one of said plurality of word lines in response to said address signal, and
- supplying a voltage across said selected bit line and said selected word line whereby said electric charges are discharged from said floating gate region of one of said memory cells having said first conduction terminal and said control terminal respectively connected to said selected bit line and said selected word line.
Dependencies are inferred from the claim text.