5B6B coding rule inverse conversion circuit for digital transmission

A mark rate detecting circuit in a data transmission system utilizing the 5B6B code as a code format on a transmission line, comprising;

• a first mark rate detecting circuit for detecting a mark rate of the upper three bits in a six bit signal which has been converted by the 5B6B coding rule conversion method, said first mark rate detecting circuit including a first NOR circuit, an AND circuit, and an EOR circuit receiving in parallel said upper three bits;
• an inverter connected to receive an output of said EOR circuit;
• and a second NOR circuit and a third NOR circuit receiving the outputs of said first NOR circuit and said AND circuit;
• said EOR circuit supplying an output to said second NOR circuit and to said inverter;
• said inverter supplying its output to said third NOR circuit, such that said third NOR circuit receives a signal corresponding to the inverted output of said EOR circuit;
• a second mark rate detecting circuit for detecting the mark rate of the lower three bits of th six bits, said second mark rate detecting circuit including a first NOR circuit, an AND circuit, and an EOR circuit receiving in parallel said upper three bits;
• an inverter connected to receive an output of said EOR circuit;
• and a second NOR circuit and a third NOR circuit receiving the outputs of said first NOR circuit and said AND circuit;
• said EOR circuit supplying an output to said second NOR circuit and to said inverter;
• said inverter supplying its output to said third NOR circuit, such that said third NOR circuit receives a signal corresponding to the inverted output of said EOR circuit;
• and
• a 6-bit mark rate deciding circuit for deciding the mark rate of the six bits, responsive to the mark rate detected by the first mark rate detecting circuit and the second mark rate detecting circuit, said 6-bit mark rate deciding circuit including a plurality of AND circuits disposed in parallel, said plurality of AND circuits being connected to receive outputs of said second and third NOR circuits of said first mark rate detecting circuit and said second and third NOR circuits of said second mark rate detecting circuit, and wherein one of said plurality of AND circuits receives the output from said first NOR circuit of said first mark rate detecting circuit, and wherein another one of said plurality of AND circuits receives the output from said first NOR circuit of said second mark rate detecting circuit.

A 5B6B coding rule inverse conversion circuit in a data transmission system utilizing the 5B6B code as a code format on a transmission line, comprising:

• a first two bit mark rate detecting circuit for detecting a mark rate of upper two bits in a six bits signal which has been converted by the 5B6B coding rule conversion method and separately outputting an upper bit and a lower bit of said upper two bits in the six bits signal;
• a second two bit mark rate detecting circuit for detecting the mark rate of intermediate two bits of the six bits and separately outputting an upper bit and a lower bit of said intermediate two bits in the six bits signal;
• a third two bit mark rate detecting circuit for detecting the mark rate of lower two bits for the six bits and separately outputting an upper bit and a lower bit of said lower two bits in the six bits signal;
• a first decoder having three input terminals respectively receiving the upper bit separately output from each of said first, second, and third two bit mark rate detecting circuits, for generating a logical signal of eight patterns from the logical signal of the upper bit of respective 2-bit logical signals detected by each of said first, second, and third two bit mark rate detecting circuits, indicating the mark rate detected by each of said first, second, and third two bit mark rate detecting circuits;
• a second decoder having three input terminals respectively receiving the lower bit separately output from each of said first, second, and third two bit mark rate detecting circuits, for generating the logical signal of eight patterns from the logical signal of the lower bit of the respective 2-bit logical signals detected by each of said first, second, and third two bit mark rate detecting circuits, indicating the mark rate;
• and
• a 6-bit mark rate deciding circuit for deciding mark rates of the six bits, responsive to a total of 16 patterns generated by the first and second decoders.