Loading patent…
AssigneeQuickLogic Corporation
InventorsJohn M. Birkner, David T. Martin, Richard J. Wong
Estimating the term…
A method for determining an electrical characteristic (such as a resistance) of an antifuse of a programmable device. The method comprises the steps of: 1) before the antifuse is programmed, determining an electrical characteristic (such as a voltage, current and/or resistance) of a first conductive path which includes a series element disposed electrically in series with a parallel element, the parallel element being controlled to be substantially conductive, the parallel element being disposed electrically in parallel with the unprogrammed antifuse; 2) after programming of the antifuse, determining an electrical characteristic (such as a voltage, current and/or resistance) of a second conductive path including the series element disposed electrically in series with the programmed antifuse when the parallel element is controlled to be substantially nonconductive; 3) determining an electrical characteristic (such as a voltage, current and/or resistance) of a third, conductive path through the series element, and through the programmed antifuse and the parallel element, the parallel element being controlled to be substantially conductive; and 4) determining the electrical characteristic (such as a resistance) of the antifuse based on the above three determinations in 1), 2) and 3). The method is usable to determine whether or not programmed antifuses of a programmable device have low enough resistances to meet desired reliability criteria.
A method of determining an electrical characteristic of an antifuse of a programmable device, said programmable device comprising a series element, a parallel element and said antifuse, said method comprising the steps of:
A method of determining a resistance of an antifuse of a programmable device, said programmable device comprising a series element, a parallel element and said antifuse, said method comprising the steps of:
An apparatus for determining a resistance of an antifuse of a programmable device, comprising:
An apparatus for programming an antifuse of a programmable device, a pass transistor of said programmable device being disposed electrically in parallel with said antifuse, a series element of said programmable device being disposed electrically in series with said antifuse, said pass transistor having a resistance P when said pass transistor is controlled to be substantially conductive, said series element having a resistance S when said series element is substantially conductive, said antifuse having a resistance L after said antifuse is programmed to be substantially conductive, said resistance P and said resistance L being different resistances, said apparatus having a current measuring capability to resolve a difference in current between each combination of the following currents I1, I2 and I3:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
No related US applications are recorded in the indexed filing history.
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: in fuses
In which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of…
Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation: detection or location of defective…
Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals: marginal testing, e.g. race, voltage…
Term ended 27 Aug 2012 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
This invention relates to programmable devices which comprise antifuses. More particularly, this invention relates to determining an electrical characteristic of an at least partially programmed antifuse of a programmable device such as a field programmable gate array.
A field programmable device (or a so-called "field programmable gate array") is a versatile integrated circuit chip, the internal circuitry of which may be configured by an individual user to realize a user-specific circuit. To configure a field programmable device, the user configures an on-chip interconnect structure of the field programmable device so that selected inputs and selected outputs of selected on-chip logic components are connected together in such a way that the resulting circuit is the user-specific circuit desired by the user.
FIG. 1A-1B is a top down simplified diagram illustrating a corner portion of a field programmable device. Three vertical routing channels A-C and three horizontal routing channels D-F separate nine universal logic modules M1-M9. These nine logic modules are arranged in a three-by-three matrix. Each logic module may, for example, comprise logic components such as digital logic gates, digital sequential logic circuitry, and other logic circuitry.
FIGS. 1A-1B are a top down simplified diagram illustrating a corner portion of a large field programmable device.
FIG. 2 is a cross sectional view of one possible embodiment of a cross antifuse the resistance of which is determinable using a method of the present invention.
FIG. 3 shows the programming of a pass antifuse L3 in the field programmable device of FIG. 1A-1B.
FIGS. 5A and 5B illustrate a step in accordance with one embodiment of the present invention. FIG. 5A illustrates a conductive path extending from a Vcc+ voltage source to a GND voltage source. In the embodiment shown in FIGS. 5A and 5B, a first programming driver PD1 is powered from a Vcc+ voltage and from a ground voltage GND and is controlled to drive wire W13 with the ground voltage. A second programming driver PD2 is also powered from the Vcc+ voltage and from the ground voltage GND and is controlled to drive wire W16 with the Vcc+ voltage. The difference in electrical potential between the Vcc+ voltage and the ground voltage GND is greater than the magnitude of Vcc, the normal circuit operating supply voltage but is typically less than the magnitude of a programming voltage Vpp used to program antifuses. The Vcc+ voltage source is, in some embodiments, an off-chip voltage source which supplies the Vcc+ voltage to the programmable device via one terminal (such as a programming current pin) of the integrated circuit package of the programmable device. If, for example, only one current path is formed on-chip, then the magnitude of the total current supplied to the programming current pin will be indicative of the current flowing in the current path on-chip. The source of the ground voltage GND is, in some embodiments, also an off-chip voltage source.
As illustrated in FIG. 5A, a conductive path is formed from the source of the Vcc+ voltage, into the integrated circuit chip package of the programmable device, through programming driver PD2, through wire W16, through conductive pass transistor P12, through wire W15, through conductive pass transistor P11, through wire W14, through conductive pass transistor P10, through wire W13, through programming driver PD1, and from the integrated circuit chip to an off-chip source of the ground voltage GND. In this illustrative conductive path, all the antifuses L3, L4 and L5 are unprogrammed.
FIG. 5B is a circuit diagram illustrating the conductive path of FIG. 5A. Parallel resistance P represents the resistance of conductive pass transistor P10 whereas series resistance S represents the resistance of the remainder of the conductive path. With transistors P10, P11 and P12 turned on to be at least substantially conductive, with programming driver PD2 outputting the Vcc+ voltage, and with programming driver PD1 outputting the ground voltage GND, the current I1 flowing from the source of the known Vcc+ voltage to the source of the known ground voltage GND through the circuitry of the programmable device is measured. Accordingly, the following relationship is determined. ##EQU1## whereas S and P are each unknown resistances.