Formatter circuit
AssigneeHewlett-Packard Company
InventorUlrich Knoch
Life of this patent
Estimating the term…
Abstract
A formatter circuit for an integrated circuit tester comprises at least one edge-triggered toggle flip-flop, which may be constituted of an EXOR gate and a D flip-flop. This allows to build an event-driven formatter with broad flexibility and "change timing" capability. The basic toggle flip-flops may be cascaded by further EXOR gates, in order to perform more complex functions and to combine several data input signals or clock signals.
Claims9
A formatter circuit for an integrated circuit tester receiving at least two data signals, at least two timing signals, and providing at least one pulse sequence for application to at least one pin of a device under test, said formatter circuit comprising:
- at least two edge-triggered, toggle flip-flop means, each said toggle flip-flop means having a clock input, a data input and an output, wherein said timing signals are fed to clock inputs of each said toggle flip-flop means respectively and said data signals are fed to data inputs of each said toggle flip-flop means respectively, each said toggle flip flop means (i) inverting a level on said output in response to a first direction edge transition of a said timing signal when said data input is in a true state and (ii) maintaining unchanged a level on its output when said data input is in a false state, irrespective of edge transitions of a said timing signal, and wherein outputs of said toggle flip-flop means are fed to inputs of EXOR circuitry.
A method for formatting data in an integrated circuit tester, comprising the steps of:
- feeding at least two data signals to data inputs of at least two edge-triggered, toggle flip-flops each said toggle flip-flop having a timing signal input, a data signal input and an output and (i) inverting a level on said output in response to a first sense edge transition of a timing signal when a data signal input manifests a true state and (ii) maintaining unchanged a level on said output when said data signal input manifests a false state, irrespective of edge transitions of a timing signal on said timing signal input;
- and
- feeding at least two timing signals to clock inputs of said edge-triggered toggle flip-flops;
- and feeding outputs of said toggle flip-flops to inputs of EXOR circuitry.
Dependencies are inferred from the claim text.