Semiconductor integrated circuit device
AssigneeKabushiki Kaisha Toshiba
InventorsTakahiko Hara, Syuso Fujii
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AssigneeKabushiki Kaisha Toshiba
InventorsTakahiko Hara, Syuso Fujii
Estimating the term…
In a CMOS-DRAM, an n-type silicon substrate has a p-type well formed therein, and a DRAM cell array is formed in the p-type well. In a period immediately after an external power supply is turned on, the p-type well is in a substantially floated condition. A predetermined time after the external power supply is turned on, the p-type well is applied with a predetermined DC voltage generated by a well voltage generating circuit. The CMOS-DRAM has a selective grounding circuit. When the external power supply is turned on, the selective grounding circuit forcibly grounds the plate electrode of the DRAM cell array for a predetermined period of time. Therefore, an increase in the well voltage at the cell array region, which increase may occur due to the capacitive coupling, is prevented when the power supply is turned on. Accordingly, adverse effects arising from the increase in the well voltage are prevented.
A DRAM comprising:
A DRAM comprising:
Dependencies are inferred from the claim text.