Back to results
US 5,293,053 AGranted
Elevated CMOS
AssigneeTexas Instruments Incorporated
InventorsSatwinder S. Malhi, Ravishankar Sundaresan, Shivaling S. Mahant-Shetti
Life of this patent
Estimating the term…
Abstract
A new class of CMOS integrated circuits, wherein the PMOS and NMOS devices are both configured as vertical transistors. One trench can contain a PMOS device, an NMOS device, and a gate which is coupled to control both the PMOS device and the NMOS device. Latchup problems do not arise, and n+ to p+ spacing rules are not required.
Claims16
An integrated circuit device comprising:
- a dielectric layer having a recess therein;
- an n-type insulated gate vertical-channel field effect transistor having its vertical-channel within, and on one side of said recess;
- a p-type insulated gate vertical-channel field effect transistor having its vertical-channel within, and on another side of said recess opposite from the vertical-channel of said n-type insulated gate vertical-channel field effect transistor;
- and
- a control gate disposed in said recess between said n-type and p-type insulated gate vertical-channel field effect transistors connected to control current flow in said vertical-channel of both said n-type and said p-type insulated gate vertical-channel field effect transistors.
2 more elements
An integrated circuit device comprising:
- a dielectric layer including therein a recess with substantially vertical sidewalls;
- a first insulated gate field effect transistor disposed within and adjacent to a first sidewall of said recess, said first insulated gate field effect transistor having a first source/drain and a second source/drain separated from one another vertically along said first sidewall of said recess by a channel region and a second insulated gate field effect transistor disposed within and adjacent to a second sidewall of said recess, said second insulated gate field effect transistor having a first source/drain and a second source/drain separated from one another vertically along said second sidewall of said recess by a channel region, wherein said first and second insulated gate field effect transistors are of complementary conductivity types;
- and
- a control gate disposed within said recess between the channel regions of said first and second insulated gate field effect transistors to control current flow in both said first and second transistors.
1 more element
Dependencies are inferred from the claim text.