Back to results
US 5,292,687 AGranted
Process for lay-out of a semiconductor integrated circuit
AssigneeNEC Corporation
InventorTomoaki Isozaki
Life of this patent
Estimating the term…
Abstract
A pad is provided outside a pad block. The most appropriate position is determined for the pad which is connected to the pad block. The pad block is arranged to be most appropriate in position relative to the pad, and a coordinate of the pad block is determined to be used for interconnection of internal regions of the pad block.
Claims6
A process for lay-out of a semiconductor integrated circuit, comprising the steps of:
- determining a coordinate of a pad position which is most appropriate in accordance with a lead frame for packaging said semiconductor integrated circuit and a chip size of said semiconductor integrated circuit;
- arranging a pad at said coordinate;
- connecting said pad to a pad block, said pad block being positioned to be most appropriate relative to said pad;
- determining a coordinate of said pad block;
- and
- connecting internal regions of said pad block in accordance with said coordinate of said pad block.
3 more elements
Dependencies are inferred from the claim text.