US 5,292,677 A · Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts

Abstract

An etch stop layer is deposited on a DRAM wafer after formation of the PMOS and NMOS transistors and A.A's. After deposition of oxide 1, a first mask and etch process is used to form the capacitor container and remove the oxide 1 and etch stop at the future poly 1 and cell poly contacts. After deposition of the capacitor, a second mask and etch removes the capacitor layers at the future poly 1 contact. After deposition of oxide 2 and a poly etch stop layer, a third mask and etch process forms the bit line contact region through the cell poly, and the poly 1 and cell poly contact region. The etch is made through the cell poly at the bit line contact and a thin oxide is deposited and etched to form cell poly spacers that don't close off the active area. An oxide etch goes to the etch stop layer at the bit contact region, to the poly 1 at the future poly 1 contact, and to the cell poly at the future cell poly contact. After etch of the etch stop at the future bit line contact, the contacts are formed.

Claims18

Dependent claims

A method of fabricating a integrated circuit dynamic random access memory (DRAM), said DRAM comprising a semiconducting wafer having:

a semiconducting substrate;
a plurality of transistors formed on said substrate, each transistor including a gate conducting layer;
a capacitor formed on said substrate and having a capacitor first conducting layer, a capacitor dielectric layer, and a capacitor second conducting layer;
an active area on said substrate adjacent one of said transistors;
a bit line contact contacting said active area;
and a gate contact contacting said gate conducting layer;
said method comprising the steps of:
employing a first etch stop layer to self align said capacitor first conducting layer contact to said gate conducting layer;
employing said first etch stop layer to self align said bit line contact to said gate conducting layer;
and
utilizing a single photo-mask and etch process to define said bit line contact and etch to said active area and to define said gate contact and etch to said gate conducting layer.

8 more elements

A method of fabricating a integrated circuit dynamic random access memory (DRAM), said DRAM comprising a semiconducting wafer having a semiconducting substrate, a plurality of transistors formed on said substrate, each including a gate conducting layer, a capacitor formed on said substrate and having a capacitor first conducting layer, a capacitor dielectric layer, and a capacitor second conducting layer, an upper insulating layer covering said capacitor second conducting layer, an active area on said substrate adjacent one of said transistors, a bit line contact contacting said active area, a gate contact contacting said gate conducting layer, and a capacitor conducting layer contact, said method comprising the step of:

providing a single photo-mask;
creating a resist layer on said wafer and using said single photo-mask to pattern said resist layer to define said bit line contact and said capacitor conducting layer contact;
and
etching said pattern into said upper insulating layer and through said capacitor second conducting layer to said active area to form a bit line contact region while etching said pattern into said upper insulating layer to said capacitor second conducting layer to form a capacitor conducting layer contact region.

1 more element

A method for fabricating an integrated circuit comprising the steps of:

a) providing an integrated circuit wafer having:
a semiconducting substrate;
a plurality of transistor gate members each comprising a gate insulating layer formed on said substrate and a gate conducting layer on said gate insulating layer;
and first and second active areas on said semiconducting substrate;
b) forming a first etch stop layer on said wafer, covering said transistor gate members and said active areas;
c) creating a lower insulating layer on said wafer;
d) utilizing a first photo-mask and etch process to define a capacitor container in said lower insulating layer and said first etch stop layer above said first active area and a gate conducting layer contact region in said lower insulating layer and said etch stop layer above a first transistor gate member;
e) forming a capacitor first conducting layer in said capacitor container and in said transistor gate conducting layer contact region, said capacitor first conducting layer in electrical contact with said first active area;
f) forming a capacitor dielectric layer on said capacitor first conducting layer;
g) forming a capacitor second conducting layer on said capacitor dielectric layer;
h) utilizing a second photo-mask and etch process to remove said capacitor second conducting layer, said capacitor dielectric layer, and said capacitor first conducting layer from said gate conducting layer contact region;
i) creating an upper insulating layer on said wafer;
j) utilizing a third photo-mask and etch process to define a bit line contact region above said second active area and to define a gate conducting layer contact region above said first transistor gate member;
k) creating a capacitor insulating spacer between said capacitor second conducting layer and said bit line contact region;
and
l) creating a bit line contact in electrical contact with said second active area and a gate conducting layer contact in electrical contact with said gate conducting layer of said first transistor gate member.

13 more elements

A method of fabricating an integrated circuit comprising a capacitor and a transistor, said method comprising:

providing an integrated circuit wafer with a semiconducting substrate having:
a gate conducting layer forming the gate of said transistor, said gate conducting layer made of a material which has selectivity in both a first etch process and a second etch process;
an active area, and an insulating spacer isolating said active area from said transistor gate, said insulating spacer made of a material which has selectivity in a said second etch process;
forming an etch stop layer on said wafer, said etch stop layer made of a material having selectivity in said first etch process and being etchable in said second etch process, said etch stop layer covering said active area;
forming a lower insulating layer on said wafer, said lower insulating layer made of a material which is etchable in said first etch process;
using a container photo-mask and first etch process to etch through said lower insulating layer and a second etch process to etch away said etch stop layer to form a capacitor container while removing said lower insulating layer and said etch stop layer from above a least a portion of said gate conducting layer;
forming a capacitor cell in said capacitor container;
forming an upper insulating layer on said wafer, said upper insulating layer made out of a material which is etchable in said first etch process;
using a contact photo-mask and said first etch process etch to etch through said upper and lower insulating layers and stop on said etch stop layer above said active area and on said portion of said gate conducting layer;
etching away said etch stop layer above said active area using said second etch process;
and
forming a contact contacting said portion of said gate conducting layer and a contact contacting said active area.

9 more elements

Dependencies are inferred from the claim text.

Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts

Life of this patent

Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts

Life of this patent

Abstract

Claims18