Method for forming a metallurgical interconnection layer package for a multilayer ceramic substrate

A method of fabricating on a multilayer ceramic body, a metallurgical interconnection layer system for interconnection of a plurality of large scale integrated circuit semiconductor chips, said ceramic body including conductive circuitry and vias therein, the vias extending from said conductive circuitry and forming a planar surface with said ceramic body, said method comprising:

• screen printing, drying and firing a blanket layer of etchable conductive metal paste on said ceramic body;
• depositing a layer of photoresist over said metal paste;
• exposing and developing said photoresist to form a fine line circuit pattern including exposed areas between the fine line pattern;
• etching the exposed areas of the fired layer of metal paste to form a circuit pattern, and removing the developed photoresist layer;
• screen printing, drying and firing a layer of dielectric material over said circuit pattern, said layer of dielectric material having via holes;
• filling the via holes with a conductive paste, and drying and firing said conductive paste;
• repeating the aforesaid process steps to build up the necessary levels of the interconnection pattern;
• screen printing, drying and firing a top layer of etchable conductive paste;
• said metal paste including conductivity imparting powders, glass frit, and a vehicle which includes a nonvolatile resin and volatile solvent,
• depositing a layer of photoresist on the surface of said conductive paste, exposing said photoresist to form a fine line top circuit pattern, and developing the photoresist;
• and
• etching the exposed areas of the layer of etchable conductive paste, and removing the remaining photoresist.