US 5,291,615 AGranted

Instruction pipeline microprocessor

AssigneeKabushiki Kaisha Toshiba

InventorKosei Okamoto

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Abstract

An instruction pipeline type microprocessor comprises an operation execution section consisting of a first operation execution section for executing instructions having no memory operand, a second operation execution section for executing instructions having a memory operand, and a third operation execution section for executing floating point instructions. A general purpose register is provided consisting of a second register group for storing data processed as a result of execution by the operation execution section in the form of a flow of programs and a first register group for storing processed data as the result of a look-forward execution of instructions which can be processed by the operation execution section. Compare logic determines whether or not succeeding instructions have been executed. The processed data held in the first register group is provided to the second register group so as to facilitate execution in the predetermined program order.

Claims6

Dependent claims

An instruction pipeline type microprocessor, comprising:

(a) means for fetching, decoding and determining a plurality of different kinds of decoded instructions and sending said plurality of different kinds of decoded instructions in accordance with said determined different kinds;
(b) a plurality of operation execution sections for receiving said decoded instruction according to said determined different kinds and respectively executing said plurality of different kinds of decoded instructions simultaneously, wherein each of said plurality of operation execution sections includes an instruction register having at least an instruction address holding field indicative of an address of an instruction decoded in a program and a destination register designation field;
(c) first storing means for storing processed data, said data resulting from having executed in a look-forward manner, instructions capable of processing by said plurality of operation execution sections without waiting for execution results of preceding instructions, said first storing means including a plurality of tag bits;
(d) second storing means for storing processed data resulting from execution by said operation execution sections of instructions executed in predetermined program order;
and
(e) compare means for comparing each datum from said operation execution sections in terms of a sequence in which the execution is completed and for sending, said datum being an address received from the address holding field of said each instruction register, based on the sequence of completion of the execution and the predetermined program order, the processed data directly to at least one of the second storing means and the first storing means, said processed data stored in said first storing means being transferred to said second storing means in the predetermined program order according to compare results and contents of said tag bits,
wherein said compare means comprises a comparator for comparing each said datum, and for producing signals indicative of the result of the comparisons and for sending said signals to said first storing means, said tag bits being determined by said signals from the comparator.

4 more elements

An instruction pipeline type microprocessor, comprising:

(a) means for fetching a plurality of instructions;
(b) means for decoding said plurality of instructions;
(c) means for determining types of a plurality of decoded instructions and for sending said decoded instructions according to a determined type;
(d) a plurality of operation execution sections, each for executing a specific type of instruction, receiving said decoded instructions according to said determined type, said operation execution sections simultaneously executing said decoded instructions, each of said plurality of operation execution sections including an instruction register having at least an instruction address holding field indicative of an address of an instruction decoded in a program and a destination register designation field;
(e) compare means for comparing each address of said instructions contained in each instruction address holding field of respective said operation execution sections, thereby indicating a sequence in which instruction execution is completed and outputting compare results indicating said sequence;
(f) first storing means for storing first processed data according to a compare result that an address of one of said instructions was not a minimum, said first processed data resulting from having executed instructions in a look ahead manner;
(g) second storing means for storing second processed data according to another compare result that an address of one of said instructions was a minimum, said second processed data resulting from execution by at least one of said operation execution sections of instructions executed in predetermined program order;
and
(h) means for transferring said processed data stored in said first storing means to said second storing means in response to said compare results, thereby storing data in said second storing means in the predetermine program order.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/974,328Filed 10 Nov 1992 · continuation
Priority: JP 63-19878911 Aug 1988
Granted: 1 Mar 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 9/3863
Recovery, e.g. branch miss-prediction, exception handling: using multiple copies of the architectural state, e.g. shadow registers
G06F 9/3836
Concurrent instruction execution, e.g. pipeline or look ahead: instruction issuing, e.g. dynamic instruction scheduling or out of order…
G06F 9/3867
Concurrent instruction execution, e.g. pipeline or look ahead: using instruction pipelines
G06F 9/3885
Concurrent instruction execution, e.g. pipeline or look ahead: using a plurality of independent parallel functional units