Real-time, concurrent, multifunction digital signal processor subsystem for personal computers

A personal computer comprising:

• a main memory for storing application programs:
• a first processor for executing said application programs;
• a plurality of application specific hardware (ASH) devices;
• a general purpose digital signal processing subsystem (DSPSS) connected to said ASH devices;
• and
• bus means interconnecting said first processor, said main memory, and said DSPSS;
• said DSPSS comprising
• a plurality of ports connected to said ASH devices for transmitting analog signals and digital signals between said ASH devices and said DSPSS,
• converter means for converting said analog signals into digital operands,
• an instruction store connected to said DSP for storing a plurality of signal processing tasks for execution by said DSP,
• a data store connected to said DSP and to said bus means so that said DSP and said first processor can independently access said data store, said data store being further connected to said ports and to said converter means for storing said digital operands and said digital signals,
• a digital signal processor (DSP) for processing said digital signals and said digital operands, said DSP comprising an arithmetic logic unit and a multiplication unit for executing tasks to process said digital operands and said digital signals, and
• control means connected to said DSP for operating said DSP and concurrently executing a plurality of said signal processing tasks in response to execution of said application programs by said first processor;
• said control means comprising
• a scheduling clock for generating a plurality of scheduling interrupts at fixed time intervals;
• a plurality of task control blocks (TCBs) stored in said data store, there being a different TCB associated with each task, each TCB containing a plurality of fields for storing, for the associated task, 1) a frame defining a scheduling period between successive scheduling of said associated task, 2) a scheduling count defining when the associated task is to be next scheduled, 3) DSP information for restoring said DSP when an interrupted task is next executed, and 4) an instruction address at which to begin initial execution of said associated task;
• a background executor for maintaining a queue of tasks scheduled for execution;
• a foreground executor that is periodically executed in response to said scheduling interrupts for scheduling said tasks, said foreground director including means for 1) saving DSP information from a task being interrupted, 2) searching said unordered list of TCBs to find a TCB whose count field has reached a predetermined value, 3) adding the task associated with such TCB, to said queue of tasks, 4) updating said count field, in said TCB of the task added to said queue, by adding said frame to said count, 5) ordering said tasks in said queue according to which tasks have the lowest counts in said TCBs associated therewith, with the task having the lowest count being at a head of said queue, and 6) passing control to said background executor;
• said background executor including means, operative in response to receiving control from said foreground executor, for passing control to said task at said head of said queue for execution thereof, for removing said task from said queue upon completion of execution thereof, and for passing control to the next task in line in said queue when another task has completed execution.