Transparent system interrupts with automated halt state restart

An improved microprocessor system comprising a central processing unit (CPU) coupled to at least one memory unit for executing an operating system and at least one application program comprising a plurality of said CPU's instructions, said CPU further having at least two modes of program execution, a real mode and a protected mode, and at least one interrupt for interrupting program execution, wherein the improvement to said microprocessor system comprises:

• (a) said memory units having a dedicated memory area for storing an interrupt processing program, processor state data of said CPU, and a halt indicator, said dedicated memory area being not mapped as part of main memory space thereby keeping said dedicated memory area inaccessible to said operating system and application programs, said processor state data comprising an instruction pointer and a prior instruction pointer pointing to first and second instructions of said operating system and application programs respectively, said first instruction being an instruction to be executed next by said CPU and said second instruction being an instruction executed by said CPU before an interrupt, said halt indicator indicating whether said CPU is interrupted from an halt state that resulted from execution of a Halt instruction, said instructions comprising said Halt instruction;
• (b) said interrupts having a System Supervisor Interrupt (SSI) for interrupting execution of said operating system and said application programs, switching in and mapping said dedicated memory area to a pre-determined segment of said main memory space, storing said processor state data of said CPU into said dedicated memory area including said instruction and prior instruction pointers, switching said CPU into said real mode of execution, determining if said CPU is being interrupted from said halt state, conditionally setting said halt indicator to so indicate if said CPU is being interrupted from said halt state, and starting execution of said interrupt processing program, said SSI being unmaskable by said operating system and said application programs, and having a higher priority than other interrupts;
• (c) said instructions having a Resume instruction for restoring said saved processor state data from said dedicated memory area to said CPU including said instruction and prior instruction pointers, checking said halt indicator to determine if it is set, conditionally decrementing said restored instruction pointer to said restored prior instruction pointer if said halt indicator is set, switching out and unmapping said dedicated memory area to said main memory space, and resuming execution of said operating system and said application programs;
• thereby allowing said CPU to be interrupted reliably and automated halt state restart be provided to said interrupt service program in a manner transparent to said operating system and said application programs.