Apparatus and method for synchronization of access to main memory signal groups in a multiprocessor data processing system

A method of modifying a data element in a main memory unit of a data processing system, said main memory unit having locations, said locations being either in a locked condition or an unlocked condition, said data processing system having a plurality of central processing units and said main memory unit, comprising the steps of:

• a) providing to each one of said central processing units a plurality of instructions for execution, at least one of said instructions being an interlock instruction, execution of each of said plurality of instructions causing the central processing unit that executes said instruction to transfer one of said data elements from a location in said main memory unit to said central processing unit, modify said data element, and transfer said modified data element back to said main memory location;
• b) responding to each one of said instructions executed by one of said central processing units by (1) granting said one central processing unit interlock access to said main memory location by placing said main memory location in said locked condition if said executed instruction is an interlock instruction and said main memory location is in said unlocked condition, (2) denying said one central processing unit access to said main memory location if said executed instruction is an interlock instruction and said main memory location is in said locked condition, (3) granting said one central processing unit non-interlocked access to said main memory location without placing said one memory location in said locked condition if said executed instruction is not an interlock instruction, and (4) causing said data element to be transferred from said main memory location to said one central processing unit to be modified if said one central processing unit has been granted access to said main memory location;
• said one central processing unit further responding to said executed instruction by transferring said modified data element from said one central processing unit to said main memory location, and, if said executed instruction is an interlock instruction, placing said main memory location in said unlocked condition;
• and
• c) executing said instruction by said one central processing unit without interruption from another of said central processing units.

A data processing system including a main memory unit and a plurality of data processing units comprising:

• a) means for providing to each one of said data processing units a plurality of sequences of instructions stored in predetermined locations in said main memory unit for execution;
• and
• b) control means for executing one of said instruction sequences in response to a modify instruction from one of said data processing units without interruption from another of said data processing units,
• wherein, (1) if said modify instruction is an interlock instruction and said main memory unit is not interlocked, said one data processing unit:
• interlocks said main memory unit and prevents another one of said data processing units from interlocking said main memory unit,
• modifies a data element in said main memory unit, and
• releases said main memory unit interlock;
• (2) if said modify instruction is an interlock instruction and said main memory unit is interlocked, said one data processing is denied access to said main memory;
• and
• (3) if said modify instruction is not an interlock instruction, said one data processing unit modifies a data element in said main memory unit without interlocking said main memory unit.

A data processing system comprising a plurality of central processing units and main memory units, each one of said central processing unit having:

• a) register means connected to each of said central processing units for receiving data elements from one of said main memory units and for storing said data elements therein;
• b) transfer means connected to each of said central processing units for transferring a data element between one of said main memory units and said register means of one of said central processing units;
• c) combining means for logically combining said transferred data element stored in said register means with a mask signal group stored in a second register means of said one central processing unit to form a modified data element;
• d) interlock means associated with each of said main memory units for controlling interlock access to at least one data element;
• and
• e) execution means for executing an instruction included in a plurality of instructions provided for each of said central processing units and that includes an interlock instruction and a second instruction, said one central processing unit selecting between said interlock instruction and said second instruction,
• execution of said interlock instruction:
• causing said interlock means to grant said one central processing unit interlock access to said data element and prevent interlock access to said data element by another of said central processing units when no other of said central processing units has interlock access to said data element and causing said interlock means to deny said one central processing unit interlock access to said data element when another of said central processing units has interlock access to said data element;
• and, when said one central processing unit has been granted interlock access, (1) causing said transfer means to transfer said data element to said register means of said one central processing unit, (2) causing said combining means to provide a modified data element, (3) causing said modified data element to replace said data element in said main memory unit, and (4) causing said interlock means to permit interlocked access to said modified data element when said modified data element has replaced said data element in said main memory unit;
• execution of said second instruction:
• causing said interlock means to grant said one central processing unit noninterlock access to said data element, causing said transfer means to transfer said data element to said register means of said one central processing unit, causing said combining means to provide a modified data element, and causing said modified data element to replace said data element in said main memory unit.