Handshake synchronization system

A method for communication between a first logic circuit operating in a first timing domain at a first clock speed, and a second logic circuit operating in a second timing domain at a second clock speed, said second clock speed being faster than said first clock speed and said second clock speed and said first clock speed having a predetermined relation to one another, said first logic circuit and said second logic circuit being coupled by a communication link, wherein said method comprises the following steps:

• a) said first logic circuit issuing a transaction request over said communication link to said second logic circuit as a result of a clock edge in said first timing domain;
• b) said second logic circuit accepting said transaction request as a result of a clock edge in said second timing domain, acceptance of said transaction request being communicated to a phase synchronization machine within said second logic circuit and to a transaction machine within said second logic circuit;
• c) said transaction machine within said second logic circuit processing said transaction request and said phase synchronization machine within said second logic circuit counting the number of clock cycles in said second timing domain during the processing of said transaction;
• d) upon completion of said transaction, said second logic circuit generating an acknowledge signal to be transmitted from said second logic circuit to said first logic circuit over said communication link as a result of a clock edge in said first timing domain, a synchronization being achieved by said phase synchronization machine using said predetermined relation between said first timing domain at said first clock speed and said second timing domain at said second clock speed in order to determine the allowable clock edges of the second timing domain to transmit said acknowledge signal to said first timing domain.

A method for communication between a first logic circuit operating in a first timing domain at a first clock speed, and a second logic circuit operating in a second timing domain at a second clock speed, said second clock speed being faster than said first clock speed and said second clock speed and said first clock speed having a predetermined relation to one another, said first logic circuit and said second logic circuit being coupled by a communication link, wherein said method comprises the following steps:

• a) said first logic circuit generating a timing signal in said first timing domain indicating valid transitions of the first clock signal;
• b) said second logic circuit receiving said timing signal and generating therefrom a clock change signal in said second timing domain;
• c) said second logic circuit applying said clock change signal to a phase synchronization machine;
• d) said second logic circuit issuing a transaction request signal over said communication link to said first logic circuit, said phase synchronization machine being operative to synchronize said transaction request signal to said first clock signal using said clock change signal;
• e) said first logic circuit accepting said transaction request and transmitting said transaction request to a transaction machine in said first logic circuit;
• f) said transaction machine in said first logic circuit processing said transaction request;
• g) upon completion of said transaction request, said first logic circuit causing a transaction acknowledge signal to be transmitted to said second logic circuit;
• and
• h) said phase synchronization machine causing said second logic circuit to synchronize an acknowledge signal from said first logic circuit to said second timing domain by using said clock change signal.