US 5,291,528 AGranted

Circuit for glitch-free switching of asynchronous clock sources

AssigneeNCR Corporation

InventorFulps V. Vermeer

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Abstract

A circuit, including a state machine, e. g. a logic array and a set of controlled storage devices, receives conditioning signals, such as reset, power failure signals and signals fed back from the storage devices, and uses the signals to determine which of a number of clock sources is to be used in a system. The state machine provides output signals which are processed by a delay circuit to ensure that switches between clock sources only occur during an inactive period of the clock signals to prevent signal glitches. The circuit's output signal controls a number of AND gates, each of which gates a particular clock signal to an output line. When a power fail condition occurs, a switch between a first clock signal and a substantially lower frequency clock signal is required to conserve power. This is achieved by first switching to a synchronized lower frequency clock signal, and then to a non-synchronized lower frequency clock signal when the first clock signal is switched off since the synchronized low frequency clock signal is lost at this time when the clock source from which the first signal is generated is switched off to conserve power. A reverse process switches back to the high frequency clock without glitches when power returns.

Claims8

Dependent claims

A switching circuit for selectively switching to an output line a first clock signal from a first clock source or a second clock signal from a second, lower frequency clock source, said second clock signal being asynchronous with respect to said first clock signal, comprising:

synchronizing means connected to said first and second clock sources for providing a third clock signal having the same frequency as said second clock signal and synchronized with said first clock signal at an output thereof;
gating means connected between said output line and the outputs of said first and second clock sources and said synchronous means;
and
control means connected to said gating means for controlling the operation thereof such that if said second clock signal is switched to said output line in place of said first clock signal, said third clock signal is gated to said output line during an inactive period of said first clock signal and causes said second clock signal to be gated to said output line during an inactive period of said third clock signal, said first clock source being rendered non-operational following its disconnection from said output line, and if said first clock signal is switched to said output line in place of said second clock signal said first clock source is rendered operational following which said third clock signal is gated to said output line during an inactive period of said second clock signal, and then said first clock signal is gated to said output line during an inactive period of said third clock signal.

1 more element

Dependencies are inferred from the claim text.