US 5,291,526 A · Digital signal reproducing apparatus for reducing influence by jitter

Abstract

A fundamental period calculation circuit calculates a fundamental period in accordance with a plurality of pulses including reproduction target pulses included in binary reproduced output signal pulses sequentially input as digital signal pulses to be reproduced. A clock generator generates a demodulation clock having the fundamental period calculated by the fundamental period calculation circuit. A phase error amount detecting circuit detects a phase error amount in accordance with a phase difference between the demodulation clock generated by the clock generator and a plurality of pulses including the reproduction target pulses. A synchronizing circuit controls the phase error amount of a generation timing of the demodulation clock by the clock generator to a predetermined value in accordance with the phase error amount detected by the phase error amount detecting circuit so that the demodulation clock generated by the clock generator is synchronized with each of the reproduction target pulses. A demodulator sequentially demodulates the binary reproduced output signal pulses in accordance with the demodulation clock from the clock generator, the demodulation clock being synchronized with each of the reproduction target pulses with the predetermined phase error amount by the synchronizing circuit.

Claims17

Dependent claims

A digital signal reproducing apparatus comprising:

fundamental period calculating means for calculating a fundamental period in accordance with a plurality of pulses including reproduction target pulses included in binary reproduced output signal pulses sequentially input as digital signal pulses to be reproduced;
clock generating means for generating a demodulation clock having the fundamental period calculated by said fundamental period calculating means and synchronized with each of the reproduction target pulses with a predetermined width;
synchronizing means for generating a sync signal representing a phase of a reproduction target pulse when a difference in phase between the reproduction target pulse and the demodulation clock is small and a sync signal representing a phase shifted by a predetermined value form a pulse of a reproduction target pulse when a difference in phase between the reproduction target pulse and the demodulation clock is large, and outputting the sync signal to said clock generating means;
and
demodulating means for sequentially demodulating the binary reproduced signal pulses in accordance with the demodulation clock form said clock generating means, the demodulation clock being synchronized with each of the reproduction target pulses with the predetermined width by said synchronizing means.

2 more elements

A digital signal reproducing apparatus comprising:

fundamental period calculating means for calculating a fundamental period in accordance with a plurality of pulses including reproduction target pulses included in binary reproduced output signal pulses sequentially input as digital signal pulses to be reproduced;
clock generating means for generating a demodulation clock having the fundamental period calculated by said fundamental period calculating means;
phase error amount detecting means for detecting a phase error amount in accordance with a phase difference between the demodulation clock generated by said clock generating means and a plurality of pulses including the reproduction target pulses;
synchronizing means for controlling the phase error amount of a generation timing of the demodulation clock from said clock generating means to a predetermined value in accordance with the phase error amount detected by said phase error amount detecting means so that the demodulation clock generated by said clock generating means is synchronized with each of the reproduction target pulses;
and
demodulating means for sequentially demodulating the binary reproduced output signal pulses in accordance with the demodulation clock from said clock generating means, the demodulation clock being synchronized with each of the reproduction target pulses with the predetermined phase error amount by said synchronizing means.

3 more elements

A digital signal reproducing apparatus comprising:

fundamental period calculating means for calculating a fundamental period in accordance with a plurality of pulses including reproduction target pulses included in binary reproduced output signal pulses sequentially input as digital signal pulses to be reproduced;
synchronizing means for generating a sync signal substantially representing a phase of each of the reproduction target pulses;
clock generating means for generating a demodulation clock having the fundamental period calculated by said PG,56 fundamental period calculating means and synchronized with each of the reproduction target pulses with a predetermined width in response to the sync signal input from the synchronizing means;
and
demodulating means for sequentially demodulating the binary reproduced output signal pulses in accordance with the demodulation clock form said clock generating means, the demodulation clock being synchronized with each of the reproduction target pulses with the predetermined width by said synchronizing means.

2 more elements

Dependencies are inferred from the claim text.

Digital signal reproducing apparatus for reducing influence by jitter

Life of this patent

Digital signal reproducing apparatus for reducing influence by jitter

Life of this patent

Abstract

Claims17