Viterbi decoding apparatus

Abstract

A Viterbi decoding apparatus for decoding received data by Viterbi decoding comprising a state metric memory circuit, a path memory circuit, and a path decode word decision circuit. The state metric memory circuit stores state metric information obtained by ACS (Adder, Comparator, Selector) processing. The path memory circuit stores path selection information provided by the ACS processing. The path decode word decision circuit weights a plurality of bits with a path decode word of each state according to its degree of likelihood based on state metric information supplied from the state metric memory circuit, cumulatively adding each path decode word obtained by the weighting operation, and comparing a cumulative value obtained by the cumulative adding operation with a preset threshold value to determine decode words. This setup provides sufficiently reliable decode words by a small amount of hardware and in a short processing time to decode, within an average information rate, convolutional codes having information amounting to 30 Mbps or more used in high-definition TV etc.

Dependencies are inferred from the claim text.