Eight-sample look-ahead for coded signal processing channels

A method of processing, in a signal processing channel, transducer-generated analog electrical signals representative of coded binary data into digital sample values, comprising the steps of:

• with a clock, generating successive clock cycles;
• with a decoder, precomputing values for the following functional expressions for a baseline check in accordance with an eight sample look ahead algorithm:
• H.sub.1 =y.sub.0 +2y.sub.1 -2y.sub.3
• H.sub.2 =y.sub.0 +2y.sub.1 +y.sub.2 -y.sub.3 -2y.sub.4
• H.sub.3 =y.sub.0 +2y.sub.1 +y.sub.2 -y.sub.4 -2y.sub.5
• H.sub.4 =y.sub.0 +2y.sub.1 +y.sub.2 -y.sub.5 -2y.sub.6
• H.sub.5 =y.sub.0 +2y.sub.1 +y.sub.2 -y.sub.6 -2y.sub.7
• where y.sub.0 is a then current sample value, and y.sub.1 -y.sub.7 are sample values in successive clock cycles following y.sub.0 ;
• and
• with the decoder, also precomputing the values of the following functional expressions for a peak-position check:
• H.sub.6 =y.sub.0 +y.sub.1 -y.sub.2 -y.sub.3
• H.sub.7 =y.sub.0 +y.sub.1 -y.sub.2 +2y.sub.4
• H.sub.8 =y.sub.0 +y.sub.1 -y.sub.2 +y.sub.4 -y.sub.5 ;
• using the decoder, executing said algorithm during each of a series of successive clock cycles to decode one successive bit of coded binary data corresponding to said current sample value and to advance to the next clock cycle with the computed next state as the new current state;
• defining each clock cycle by a clock signal that is phase locked to said analog signal;
• and
• with an analog-to-digital converter, converting the incoming analog signal to said digital sample values at a rate of one sample value per clock cycle.