Memory having distributed reference and bias voltages

A memory having distributed reference and biasing voltages, comprising:

• a plurality of bonding pads located within a central portion along a first edge of the memory, for conducting positive and negative power supply voltages;
• a first bonding pad of said plurality of bonding pads for receiving an external positive power supply voltage;
• a positive power supply voltage conductor substantially parallel to said first edge having first and second ends and coupled to said first bonding pad;
• a second bonding pad of said plurality of bonding pads for receiving an external negative power supply voltage;
• a negative power supply voltage conductor substantially parallel to said first edge having first and second ends and coupled to said second bonding pad;
• an input buffer circuit coupled to said first end of each of said positive and negative power supply voltage conductors, for providing an internal signal at a logic state responsive to a difference between an input signal and a reference voltage;
• a first bandgap reference voltage generator, coupled to said first end of each of said positive and negative power supply voltage conductors, for providing a first bandgap reference voltage;
• a bias voltage generator, coupled to said first end of each of said positive and negative power supply voltage conductors and to said amplifier, for receiving said first bandgap reference voltage and in response, providing a bias voltage to said input buffer circuit;
• a second bandgap reference voltage generator, coupled to said positive and negative power supply voltage conductors within said central portion, for providing a second bandgap reference voltage;
• and
• a reference voltage generator, coupled to each of said positive and negative power supply voltage conductors within said central portion, for receiving said second bandgap reference voltage and in response, providing said reference voltage.

A memory having distributed reference and biasing voltages, comprising:

• a plurality of bonding pads located within a central portion along a first edge of the memory, for conduction positive and negative power supply voltages;
• a first bonding pad of said plurality of bonding pads for receiving an external positive power supply voltage;
• a positive power supply voltage conductor substantially parallel to said first edge having first and second ends and coupled to said first bonding pad;
• a second bonding pad of said plurality of bonding pads for receiving an external negative power supply voltage;
• a negative power supply voltage conductor substantially parallel to said first edge having first and second ends and coupled to said second bonding pad;
• a data output buffer circuit coupled to said positive and negative power supply voltage conductors in said central portion of the memory, for providing a data output signal having a logic level determined by steering a predetermined current in response to first and second input signals;
• said data output buffer circuit comprising:
• a first resistor having a first terminal connected to said positive power supply voltage conductors in said central portion of the memory and a second terminal;
• a second resistor having a first terminal connected to said positive power supply voltage conductor in said central portion of the memory and a second terminal;
• a first transistor having a collector connected to said second terminal of said first resistor, a base for receiving said first input signal, and an emitter;
• a second transistor having a collector connected to said second terminal of said second resistor, a base for receiving said second input signal and an emitter connected to said emitter of said first transistor;
• and
• a third transistor having a collector connected to the connected emitters of said first and second transistors, a base for receiving a bias voltage, and an emitter connected to said negative power supply voltage conductor in said central portion of the memory;
• and
• a bias voltage generator coupled to each of said positive and negative power supply voltage conductors within said central portion, for providing said bias voltage;
• wherein said predetermined current is proportional to said bias voltage.

A memory having distributed reference and biasing voltages, comprising:

• first and second power supply conductors disposed substantially parallel to a first edge of the memory and having a parasitic resistance proportional to a length of said conductors, said first and second power supply conductors for receiving a first power supply voltage at a first node and providing a second power supply voltage at a second node substantially equal to said first power supply voltage minus a voltage drop due to said parasitic resistance;
• a first bandgap reference voltage generator, coupled to said first and second power supply conductors at said second node, for receiving said second power supply voltage, and for providing a first bandgap reference voltage;
• a bias voltage generator, coupled to said first and second power supply conductors at said second node, for receiving said second power supply voltage, and providing a bias voltage in response to receiving said first bandgap reference voltage;
• and
• an amplifier, coupled to said first and second power supply conductors at said second node, for receiving said second power supply voltage, and providing first and second output signals having logic levels determined by steering a predetermined current that is proportional to said bias voltage;
• wherein said bias voltage generator and said first bandgap reference voltage generator are located close to said amplifier and receive substantially the same power supply voltages in order to ensure adequate noise immunity of said at least one amplifier.