Sensing amplifier circuit for data readout from a semiconductor memory device
AssigneeSharp Kabushiki Kaisha
InventorYasuhiro Hotta
Life of this patent
Estimating the term…
Abstract
In a semiconductor memory device, two sense amplifiers are provided on one output signal line for reading data stored in a memory cell. The sense amplifiers are connected in parallel to each other. A control signal generation circuit generates a control signal so that one of the sense amplifiers which has a greater drive capability is activated during a predetermined time period after an address from which data are to be read out is changed, and that the sense amplifier having a smaller drive capability is activated during a time period other than the predetermined time period.
Claims12
A semiconductor memory device comprising:
- a plurality of sense amplifiers provided on one output signal line for reading data stored in a memory cell, said sense amplifiers being connected in parallel to each other;
- and
- a control signal generation circuit for generating a control signal by which said sense amplifiers are selectively activated.
A semiconductor memory device comprising:
- a plurality of sense amplifiers provided on one output signal line for reading data stored in a memory cell, said sense amplifiers being connected in parallel to each other, and
- a control signal generation circuit for generating a control signal by which said sense amplifiers are selectively activated,
- wherein the drive capability of one of said sense amplifiers is greater than that of another one of said sense amplifiers, and
- wherein said control signal generation circuit generates said control signal so that said one sense amplifier having a greater drive capability is activated during a predetermined time period after an address from which data are to be read out is changed, and that said another sense amplifier is activated during a time period other than said predetermined time period.
A semiconductor memory with reduced power consumption, comprising:
- first and second amplifiers connected in parallel to an output terminal of a memory cell, and
- a controller for generating a control signal for selectively activating one of the first and second amplifiers for only a portion of a memory read operation.
Dependencies are inferred from the claim text.