Read circuit of dynamic random access memory

A read circuit for a dynamic random access memory wherein a plurality of memory cells each comprising a transistor for address selection and a capacitor for storing information are arranged as a matrix at crossings of bit lines and word lines, said memory cells being divided into a plurality of memory arrays, with a column address decoder for generating a signal for selecting a common bit line for the memory arrays, and a word line selection circuit for generating a signal to select a word line in correspondence to one of the memory arrays which includes one of the memory cells to be selected, said read circuit comprising:

• a first precharger for precharging the bit lines at a first precharge potential;
• a sense amplifier for amplifying the potential of the bit lines;
• means for supplying a first activation potential necessary to activate the amplification of the sense amplifier;
• a pair of first switches controlled by a selection signal generated by the address decoder, the first switches being connected to common data lines;
• a pair of second switches each connected in series to one of the first switches, said pair of second switches being connected to a common source line, said common source line supplying a second activation potential necessary to activate the second switches, the on resistances of the pair of second switches being controlled according to the potential of the bit lines, said common data lines being connected so as to be always isolated electrically from the bit lines;
• a second precharger for precharging the common source lines of memory arrays to a second precharge potential, and for precharging the common data lines of memory arrays to a third precharge potential during the time when the common source line and the common data lines are not selected;
• and
• a third switch for connecting the common source line to the second activation potential in the selected memory array.

A read circuit for a dynamic random access memory wherein a plurality of memory cells each comprising a transistor for address selection and a capacitor for storing information are arranged as a matrix at crossings of bit lines and word lines, said memory cells being divided into a plurality of memory arrays, with a column address decoder for generating a signal for selecting a common bit line for the memory arrays, and a word line selection circuit for generating a signal to select a word line in correspondence to one of the memory arrays which includes one of the memory cells to be selected, said read circuit comprising:

• a first precharger for precharging the bit lines at a first precharge potential;
• a sense amplifier for amplifying the potential of the bit lines;
• means for supplying a first activation potential necessary to activate the amplification of the sense amplifier;
• a first switch controlled by a selection signal generated by the address decoder, the first switch being connected to a common source line, said common source line supplying a second activation potential necessary to activate the first switch, said common source line being connected to a ground potential;
• a pair of second switches connected in series to the first switch, said pair of second switches being connected to common data lines, the on resistances of the pair of second switches being controlled according to the potential of the bit lines, said common data lines being connected so as to be always isolated electrically from the bit lines;
• and
• a second precharger for precharging the common data lines of memory arrays to a second precharge potential during the time when the common source line and the common data lines are not selected, and to a third precharge potential during the time when the common source line and the common data lines are selected;
• wherein the first, second and the third precharge potentials are set so as to prevent a through current through ground.

A read circuit for a dynamic random access memory wherein a plurality of memory cells each comprising a transistor for address selection and a capacitor for storing information are arranged as a matrix at crossings of bit lines and word lines, said memory cells being divided into a plurality of memory arrays, with a column address decoder for generating a signal for selecting a common bit line for the memory arrays, and a word line selection circuit for generating a signal to select a word line in correspondence to one of the memory arrays which includes one of the memory cells to be selected, said read circuit comprising:

• a first precharger for precharging the bit lines at a first precharge potential;
• a sense amplifier for amplifying the potential of the bit lines;
• means for supplying a first activation potential necessary to activate the amplification of the sense amplifier;
• a pair of first switches controlled by a selection signal generated by the address decoder, the first switches being connected to common data lines
• a pair of second switches each connected in series to one of the first switches, said pair of second switches being connected to a common source line, said common source line supplying a second activation potential necessary to activate the second switches, said common source line being connected to the ground potential, the on resistances of the pair of second switches being controlled according to the potential of the bit lines, said common data lines being connected so as to be always isolated electrically from the bit lines;
• and
• a second precharger for precharging the common data lines of memory arrays to a second precharge potential during the time when the common source line and the common data lines are not selected, and to a third precharge potential during the time when the common source line and the common data lines are selected;
• wherein the first, second and the third precharge potentials are set so as to prevent a through current through ground.