US 5,291,448 AGranted

Zone-segregated circuit for the testing of electrically programmable memory cells

AssigneeSGS-Thomson Microelectronics S.A.

InventorBertrand Conan

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Abstract

To reduce the number of connections in an electrically programmable memory circuit, a device for the testing of the memory cells is proposed. The test consists in the reading of the current that goes through the cells to which access is had in reading mode. The testing device no longer uses specific testing connections between the cells and the corresponding input/output pins but the operational connections of the reading mode, between the reading amplifiers and the input/output buffers, in short-circuiting the input and the output of the reading amplifiers located in a zone close to the memory cells and the input/output buffers located on the peripheral zone, close to the input/output pins. The means to short-circuit the amplifiers and the buffers are respectively located in a zone close to the memory cells, and in the peripheral zone.

Claims20

Dependent claims

A device for the testing of electrically programmable memory cells of an integrated circuit comprising one or more memory arrays, each memory array including multiple bit lines, at a core thereof, a middle zone adjacent to said core, a peripheral portion adjacent to said middle zone but not adjacent to said core, and a plurality of

an associated input/output buffer, located in the peripheral zone of the circuit, and an associated reading amplifier in the middle zone of the circuit,
said input/output buffer having an input connected to an output of said reading amplifier, and having an output connected to said respective input/output pin,
said reading amplifier having an input operatively connected to a selectable one of the bit lines,
first means connected to short-circuit said input and output of said reading amplifier when commanded by a testing mode signal, these means being topographically located in the middle zone of the circuit, and
second means connected to short-circuit said input and output of said input/output buffer when commanded by said testing mode signal, these means being topographically located in the peripheral zone of the circuit.

2 more elements

A memory circuit comprising

a plurality of electrically programmable memory cells, each said cell being connected to one of a plurality of bit lines of a memory array in a core zone thereof,
a plurality of decoders and amplifiers operatively coupled to said memory array to give access thereto, said plurality of decoders and amplifiers being located in a middle zone of said memory circuit, at least a part of said middle zone being adjacent to said core zone,
a plurality of input/output buffers and a plurality of input/output nodes located in a peripheral zone of said memory circuit, at least a part of said peripheral zone being adjacent to said middle zone and none of said peripheral zone is adjacent to said core zone,
each said input/output buffer having an input connected to a respective associated one of said amplifiers and having an output connected to a respective associated one of said input/output nodes,
a plurality of first test circuit components topographically located in said middle zone, and a plurality of second test circuit components topographically located in said peripheral zone, each said first test circuit component being connected between an input and an output of a respective one of said amplifiers, and each said second test circuit component being connected between the input and the output of a respective one of said input/output buffers, and
circuitry for providing a test mode signal, when a test mode is requested, to each of said first test circuit components to short-circuit the corresponding amplifiers, and to each of said second test circuit components to short-circuit the corresponding input/output buffers.

3 more elements

Dependencies are inferred from the claim text.