Semiconductor memory device having function of controlling sense amplifiers

Abstract

A semiconductor memory device includes a memory cell array including a plurality of memory cells provided in the form of a matrix along a plurality of word lines and a plurality of pairs of bit lines, a plurality of sense amplifiers operatively connected to the plurality of pairs of bit lines, and a sense amplifier control unit operatively connected to the plurality of sense amplifiers. When one of the plurality of memory cells is selected and data writing is carried out to the selected memory cell, the sense amplifier control unit selectively inactivates only a sense amplifier corresponding to the selected memory cell among the plurality of sense amplifiers. Thus, it is possible to remove useless dissipation of write current in the data write operation to thereby decrease the dissipated power, while realizing a high speed write operation.

Dependencies are inferred from the claim text.