Semiconductor integrated circuit device

A semiconductor integrated circuit device formed on a semiconductor substrate comprising:

• first memory means including:
• a plurality of first word lines each of which extends in a first direction;
• a plurality of first data lines each of which extends in a second direction perpendicular to said first direction;
• and
• a plurality of first memory cells coupled to said first word lines and said first data lines for storing first data, each of said first memory cells comprising at least one MOS transistor;
• second memory means including:
• a plurality of second word lines each of which extends in said first direction;
• a plurality of second data lines each of which extends in said second direction;
• and
• a plurality of second memory cells coupled to said second word lines and said second data lines for storing second data, each of said second memory cells comprising at least one MOS transistor;
• a gate array including means for outputting address signals and selection signals, said gate array comprising a plurality of bipolar-CMOS basic cells each of which comprises at least one bipolar transistor and P- and N-channel MOS transistors, wherein said at least one bipolar transistor and said P- and N-channel MOS transistor of said gate array are selectively connected,
• first decoder means formed along said first direction in an area between said first memory means and said gate array, said first decoder means receiving said address signals from said gate array and selecting at least one of said first memory cells;
• second decoder means formed along said first direction in an area arranged between said second memory means and said gate array, said second decoder means receiving said address signals from said gate array and selecting at least on of said second memory cells;
• output data selecting means formed in an area arranged between said first memory means and said second memory means and receiving at least one of said first data read out from said first memory cells by said first decoder means, at least one of said second data read out from said second memory cells by said second decoder means and said selection signals from said gate array, said output data selecting means outputting output data out of at least one of said first data and at least one of said second data in predetermined bits and in predetermined combinations to said gate array.