Simultaneous read and refresh of different rows in a dram

A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells comprising:

• M rows and N columns of memory cells, wherein M and N are integers greater than 1;
• a write column line corresponding to each column;
• a read column line corresponding to each column;
• first and second write row lines corresponding to each row;
• a read row line corresponding to each row;
• each row being arranged into a top half-row of N/2 memory cells corresponding to each odd-numbered column and a bottom half-row of N/2 memory cells corresponding to each even-numbered column;
• each memory cell in the top half-row having a write column node coupled to the respective write column line, a read column node coupled to the respective read column line, a write row node coupled to the respective first write row line, and a read row node coupled to the respective read row line;
• each memory cell in the bottom half-row having a write column node coupled to the respective write column line, a read column node coupled to the respective read column line, a write row node coupled to the respective second write row line, and a read row node coupled to the respective read row line;
• a row of N/2 charge sensing amplifiers having a first input coupled to an odd-numbered write column line and a second input coupled to a next even-numbered write column;
• and
• a row of N current/voltage sensing amplifiers having an input coupled to one of the read column lines and an output for providing a digital signal.

In a memory array including two or more rows and two or more columns of memory cells, a write column line corresponding to each column, a read column line corresponding to each column, and a read row line corresponding to each row, wherein each memory cell in the array is coupled to the respective write column line, read column line, and read row line, a method for allowing simultaneous read and refresh of different rows in the array, the method comprising the steps of:

• providing first and second write row lines;
• arranging each row into a top half-row of memory cells corresponding to each odd-numbered column and a bottom half-row of memory cells corresponding to each even-numbered column;
• coupling each memory cell in the top half-row to the respective first write row line;
• coupling each memory cell in the bottom half-row to the respective second write row line;
• charge sensing each successive pair of write column lines;
• and
• current/voltage sensing each read column line;
• read-selecting an entire row of memory cells;
• reading data out of the memory cells in the read-selected row;
• normalizing each of the write column lines to a reference level;
• write-selecting, simultaneously with the step of read-selecting, another of the half-rows of memory cells from a row different than the read-selected row in order to refresh the write-selected half-row;
• and
• forcing complementary valid logic on successive pairs of write column lines responsive to the charge difference in the write column lines.

In a memory array having M rows and N columns of memory cells, wherein M and N are integers greater than 1, a write column line corresponding to each column, a read column line corresponding to each column, a write row line corresponding to each row, a read row line corresponding to each row, a method for allowing simultaneous read and refresh of the memory cells, the method comprising;

• providing a second write row line for each row of memory cells;
• arranging each row into a top half-row of N/2 memory cells corresponding to each odd-numbered column and a bottom half-row of N/2 memory cells corresponding to each even-numbered column;
• coupling a write row node of each memory cell in the top half-row to a respective first write row line;
• coupling a write row node of each memory cell in the bottom half-row to the respective second write row line;
• coupling a write column line, a read column line, and a read row line of each memory cell in each row to the respective column and row line;
• providing a row of N/2 charge sensing amplifiers having first and second inputs;
• coupling the first input of each of the charge sensing amplifiers to an odd-numbered write column line and the second input of each of the charge sensing amplifiers coupled to a next even-numbered write column;
• providing a row of N current/voltage sensing amplifiers having an input and an output;
• coupling the input of each of the current/voltage sensing amplifiers to one of the read column lines;
• providing a digital signal at the output of each of the current/voltage sensing amplifiers;
• read-selecting one of the entire rows of memory cells;
• reading data out at the output of the current/voltage sensing amplifiers respectively coupled to a read column node of each of the memory cells;
• normalizing each of the write column lines to a reference level;
• write-selecting, simultaneously with the step of read-selecting, another of the half-rows of memory cells from a row different than the read-selected row to share stored charge in the memory cell with a corresponding write column line to refresh the write-selected half-row;
• and
• forcing complementary valid levels on successive pairs of write column lines responsive to the charge difference in the write column lines.