Non-volatile programmable read only memory device having a plurality of memory cells each implemented by a memory transistor and a switching transistor stacked thereon

A non-volatile programmable read only memory device fabricated on a semiconductor substrate comprising:

• a plurality of memory cells grouped into a plurality of memory blocks and arranged in rows and columns, each of the plurality of memory blocks including a portion of the plurality of memory cells coupled in series, each of the plurality of memory cells including a parallel connection of a memory transistor disposed on a major surface of the semiconductor substrate and a switching transistor disposed over the memory transistor, the memory transistors being covered with a first inter-level insulating film, the switching transistors being thin film transistors provided on said first inter-level insulating film over the memory transistors connected in parallel therewith;
• a plurality of bit lines respectively associated with the columns of the plurality of memory cells, each bit line of the plurality of bit lines being coupled to parallel connections respectively disposed at first ends of memory blocks disposed in an associated column;
• a source line coupled to parallel connections respectively disposed at second ends of the plurality of memory blocks;
• a plurality of first word lines respectively associated with the rows of the plurality of memory cells, each of the plurality of first word lines being selectively coupled to controlling gate electrodes of each of the memory transistors;
• and
• a plurality of second word lines respectively paired with the plurality of first word lines and respectively associated with the rows of the plurality of memory cells, each of the plurality of second word lines being selectively coupled to controlling gate electrodes of each of the switching transistors.

A non-volatile programmable read only memory device fabricated on a semiconductor substrate comprising:

• a plurality of memory cells arranged in rows and columns and including memory transistors and switching transistors, each memory cell of the plurality of memory cells including a parallel connection of one of the memory transistors and one of the switching transistors;
• a plurality of bit lines respectively associated with the columns of the plurality of memory cells and selectively connectable with common drain nodes of the memory transistors and the switching transistors;
• a source line coupled to the plurality of memory cells and selectively connectable with common source nodes of the memory transistors and the switching transistors;
• first word lines respectively associated with the rows of the memory cells and selectively coupled with control gates of the memory transistors;
• and
• second word lines respectively paired with the first word lines and respectively associated with the rows of the memory cells, the second word lines being selectively coupled to gate electrodes of the switching transistors.

A non-volatile programmable read only memory device fabricated on a semiconductor substrate comprising:

• a plurality of bit lines;
• a source line;
• first word lines;
• second word lines respectively paired with the first word lines for forming a plurality of word line pairs;
• and
• a plurality of memory cells grouped into a plurality of memory blocks and arranged in rows and columns, the plurality of word line pairs being respectively associated with the rows of the plurality of memory cells, the plurality of bit lines being respectively associated with the columns of the plurality of memory cells, and the plurality of memory blocks having respective series combinations of the memory cells coupled between the bit lines and the source line;
• a plurality of block selecting transistors respectively coupled between the plurality of bit lines and the plurality of memory blocks and responsive to block selecting signals for selectively coupling the plurality of memory blocks to the plurality of bit lines.

A non-volatile programmable read only memory device fabricated on a semiconductor substrate comprising:

• a plurality of memory cells arranged in rows and columns and including memory transistors and switching transistors, each memory cell of the plurality of memory cells including a parallel connection of one of the memory transistors and one of the switching transistors, the memory transistors being formed on a major surface of the semiconductor substrate and the switching transistors being respectively provided over the memory transistors respectively connected in parallel therewith;
• a plurality of bit lines respectively associated with columns of the plurality of memory cells;
• a source line coupled to the plurality of memory cells;
• first word lines respectively associated with the rows of the memory cells and coupled to controlling gate electrodes of the memory transistors;
• and
• second word lines respectively paired with the first word lines and respectively associated with the rows of the memory cells, the second word lines being coupled to the switching transistors.

A non-volatile programmable read only memory device fabricated on a semiconductor substrate comprising:

• a plurality of memory cells grouped into a plurality of memory blocks, arranged in rows and columns, and including memory transistors and switching transistors, the plurality of memory blocks having respective series combinations of the memory cells, each memory cell of the plurality of memory cells including a parallel connection of one of the memory transistors and one of the switching transistors;
• a plurality of bit lines respectively associated with columns of the plurality of memory cells;
• a plurality of block selecting transistors respectively associated with the plurality of memory blocks and respectively coupled between the plurality of bit lines and parallel connections located at first ends of the plurality of memory blocks, the plurality of block selecting transistors being responsive to block selecting signals for selectively connecting one of the memory blocks to one of the plurality of bit lines;
• a source line coupled to parallel connections located at second ends of the plurality of memory blocks;
• first word lines respectively associated with the rows of the memory cells and selectively coupled to controlling gate electrodes of the memory transistors;
• and
• second word lines respectively paired with the first word lines and respectively associated with the rows of the memory cells, the second word lines being selectively coupled to gate electrodes of the switching transistors, one of the second word lines associated with the one of the rows of memory cells for causing the switching transistors coupled therewith to turn off, the others of the second word lines associated with the one of the rows of memory blocks causing the switching transistors coupled therewith to turn on for allowing the memory transistors associated with the switching transistors in an off-state to couple with the plurality of bit lines, respectively.