Semiconductor memory with leak-resistant bit lines
AssigneeOki Electric Industry Co., Ltd.
InventorHideki Itoh
Life of this patent
Estimating the term…
Abstract
Each of the bit lines of a semiconductor memory has an intermediate section with low electrical resistance and low electromigration resistance. If the bit line is shorted to a word line, during burn-in the electrical resistance of the intermediate section increases because of electromigration, thereby preventing excess current from leaking through the shorted bit line during subsequent use.
Claims13
A semiconductor memory comprising a plurality of bit lines, a plurality of word lines, and an equalizer for precharging said bit lines to a fixed potential, wherein each of said plurality of bit lines has a first section crossing said word lines, a second section coupled to said first section, and a third section coupled to said second section and said equalizer, and said second section has a lower electromigration resistance than said first section and said third section.
A semiconductor memory comprising a plurality of bit lines, a plurality of word lines, an equalizer for precharging said bit lines to a fixed potential, and a semiconductor substrate having a plurality of mutually isolated lightly-doped n-type areas, wherein each of said plurality of bit lines has:
- a first part crossing said word lines and making contact with a first one of said plurality of lightly-doped n-type areas;
- a second part comprising an aluminum alloy, not connected to said first part, but making contact with said first one of said plurality of lightly-doped n-type areas and a second one of said plurality of said lightly-doped n-type areas;
- and
- a third part, not connected to said first part or said second part, making contact with said second one of said plurality of lightly-doped n-type areas and coupled to said equalizer.
A semiconductor memory comprising a plurality of bit lines, a plurality of word lines, an equalizer for precharging said bit lines to a fixed potential, and a semiconductor substrate having a plurality of mutually isolated lightly-doped n-type areas, wherein each of said plurality of bit lines has:
- a first part crossing said word lines;
- a second part comprising an aluminum alloy, connected to said first part and making contact with one of said plurality of lightly-doped n-type areas;
- and
- a third part, not connected to said first part or said second part, making contact with said one of said plurality of lightly-doped n-type areas and coupled to said equalizer.
A semiconductor memory comprising a plurality of bit lines, a plurality of word lines, an equalizer for precharging said bit lines to a fixed potential, and a semiconductor substrate having a plurality of mutually isolated lightly-doped n-type areas each having a heavily-doped n-type area formed therewithin, wherein each of said plurality of bit lines has:
- a first part comprising an aluminum alloy, crossing said word lines, and making contact with one of said plurality of lightly-doped n-type areas;
- and
- a second part, coupled to said equalizer, not connected to said first part, but making contact with the heavily-doped n-type area formed within said one of said plurality of lightly-doped n-type areas.
Dependencies are inferred from the claim text.