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US 5,291,432 AGranted
Semiconductor memory device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKiyohiro Furutani
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device is provided having a read out gate for detecting and providing to a main I/O line pair the potential difference of a sub-data input/output line pair, and a write gate for transferring data of the main I/O line pair to the sub-data input/output line pair in an empty region surrounded by a sense amplifier region and a word line coupling region. By providing the read out gate and the write gate in the empty region which was not conventionally used, the access operation can be carried out at high speed without increasing the chip area of the semiconductor memory device.
Claims10
A semiconductor memory device comprising:
- a plurality of memory cell regions provided in row and column directions,
- a main data input/output line pair for transmitting externally generated data and internally generated data,
- a sub-data input/output line pair provided in a region between a pair of memory cell regions in said column direction for transmitting data to an adjacent memory cell region in said column direction,
- a plurality of data input/output control means provided in the region between the pair of memory cell regions in said column direction for carrying out data input/output control between each bit line pair of an adjacent memory cell in said column direction and said sub-data input/output line pair,
- a plurality of impedance reducing means provided between memory cell regions of said row direction for reducing the impedance of a word line,
- a plurality of read out means provided in a region surrounded by the region in which said data input/output control means are provided and by a region in which said impedance reducing means are provided for detecting and providing to said main data input/output line pair the potential difference of said sub-data input/output line pair, and
- writing means provided in a region surrounded by the region in which said data input/output control means are provided and by a region in which said impedance reducing means are provided for transferring to said sub-data input/output line pair the data of said main data input/output line pair.
4 more elements
A semiconductor memory device comprising:
- a plurality of memory cell regions arranged in row and column directions, each including a plurality of word lines provided in the row direction, a plurality of bit lines provided in the column direction, and a plurality of memory cells provided at the crossings of each word line and each bit line,
- a main data input/output line pair for transmitting externally generated data and internally generated data,
- a plurality of sub-data input/output line pairs provided between each pair of memory cell regions of said column direction, each transmitting data with respect to an adjacent memory cell region in said column direction,
- a plurality of sense amplifiers for detecting the potential of each bit line pair in said memory cell region of said column direction,
- a plurality of input/output gates provided between each pair of memory cell region of said column direction, each being connected between each bit line pair of the adjacent memory cell region in said column direction and said sub-data input/output line pair,
- a plurality of impedance reducing means provided between memory cell regions of said row direction for reducing the impedance of said word line,
- a plurality of read out means provided in a region surrounded by a region in which said input/output gates and said sense amplifiers are provided and by a region in which said impedance reducing means are provided, and
- write means provided in a region surrounded by a region in which said input/output gates and said sense amplifiers are provided and by the region in which said impedance reducing means are provided for transferring data on said main data input/output line pair to said sub-data input/output line pair.
5 more elements
A semiconductor memory device comprising:
- a plurality of memory cell regions arranged in row and column directions, each including a plurality of word lines provided in the row direction, a plurality of bit lines provided in the column direction, and a plurality of memory cells provided at crossings of each word line and each bit line,
- a main data input/output line pair for transferring externally generated data and internally generated data,
- a plurality of sub-data input/output line pairs provided between each pair of memory cell regions of said column direction, each transmitting data with respect to an adjacent memory cell region in said column direction,
- a plurality of sense amplifiers for detecting the potentials of each bit line pair of memory cell regions of said column direction,
- a plurality of input/output gates provided between each pair of memory cell regions of said column direction, each being connected between each bit line pair of an adjacent memory cell region and said sub-data input/output line pair,
- a plurality of impedance reducing means provided between memory cell regions of said row direction for reducing the impedance of said word line,
- a plurality of read out means provided in a region surrounded by a region in which said input/output gates and said sense amplifiers are provided and by a region in which said impedance reducing means are provided for detecting and providing to said main data input/output line pair the potential difference of said sub-data input/output line pair,
- write means provided in a region surrounded by the region in which said input/output gates and said sense amplifiers are provided and by the region in which said impedance reducing means are provided for transferring data of said main data input/output line pair to said sub-data input/output line pair, and
- means for controlling the potential difference of said sub-data input/output line pair to a constant potential.
6 more elements
Dependencies are inferred from the claim text.