US 5,291,425 A · Test mode setting arrangement for use in microcomputer

Abstract

A test mode setting arrangement provided in a microcomputer includes an internal memory, a plurality of pins and a central processing unit, the central processing unit being allowed to access the internal memory or an external memory depending on a logic level of a mode signal applied to the microcomputer, the arrangement basically features: a first unit for resetting the central processing unit in response to a reset control signal applied thereto, the reset control signal and the mode signal exhibiting essentially the same maximum voltage; a second unit for changing the output thereof in response to the logic level change of the mode signal, the second unit issuing an output which is applied to the central processing unit as a test mode initiating signal; and a third unit coupled to receive the mode signal and the output of the second unit, the third unit producing two signals which selects the access of the central processing unit to one of the internal and external memories.

Claims13

Dependent claims

A test mode setting arrangement provided in a microcomputer which includes an internal memory and a central processing unit, said central processing unit accessing said internal memory or an external memory depending on a logic level of an external mode signal applied to said microcomputer, comprising:

first means for resetting said central processing unit in response to an external reset control signal applied to said first means;
second means for generating an output in response to a logic level change of said mode signal;
a flip-flop coupled to be reset by said reset control signal and coupled to receive said output of said second means, said flip-flop issuing an output which is applied to said central processing unit as a test mode initiating signal;
and
logic means coupled to receive said mode signal and said output of said flip-flop, said logic means preventing said central processing unit from accessing said internal and external memories when said flip-flop issues said test mode initiating signal, said logic means producing two signals which are applied to said central processing unit to select an access by said central processing unit to one of said internal and external memories when said flip-flop does not issue said test mode initiating signal.

2 more elements

first means for resetting said central processing unit in response to an external reset control signal applied to said first means;
a counter being arranged to be reset by said reset control signal and issuing at least two outputs whose logic levels change in response to a logic level change of said mode signal;
and
logic means coupled to receive said mode signal and said outputs of said counter, said logic means producing a plurality of signals which are applied to said central processing unit to select one of plural test modes or to select an access by said central processing unit to one of said internal and external memories, depending on said mode signal and said outputs of said counter.

1 more element

Dependencies are inferred from the claim text.

Test mode setting arrangement for use in microcomputer

Life of this patent

Test mode setting arrangement for use in microcomputer

Life of this patent

Abstract

Claims13