One-chip data processor with built-in A/D converter for automatically repeating A/D conversions without instructions from a CPU

A microcomputer comprising:

• an analog-to-digital converting circuit,
• a central processing unit, and
• a data bus for allowing said central processing unit to communicate with said analog-to-digital converting unit, said analog-to-digital converting circuit comprising:
• a plurality of input nodes respectively supplied with a plurality of analog signals,
• converting means for converting each of said plurality of analog signals into digital data, and producing a finishing signal upon completion of each of said plurality of analog signals,
• a plurality of data registers, including a first register temporarily storing a designating data value for designating one of said plurality of analog signals to be converted, a second and a third register for temporarily storing function mode data for designating a fixed mode or scanning function, said first and second registers being coupled with said data bus for write-in and read-out operations;
• generating means for producing a scan designating value for sequentially designating at least analog signals selected from said plurality of analog signals, and
• controlling means responsive to said function mode data to allow automatic entry into said scanning mode upon termination of said fixed mode, and causing said converting means to sequentially convert said analog signals after one of said plurality of analog signals is converted into the digital data without rewriting said function mode data from said central processing unit, said controlling means having:
• first supplying means designating said one of said plurality of analog signals on the basis of said designating data stored in said first register, and supplying said one of said plurality of analog signals to said converting means,
• writing means for writing said digital data converted from said one of said plurality of analog signals into one of said plurality of data registers, and
• second supplying means responsive to said finishing signal produced upon completion of the analog-to-digital conversion from said one of said plurality of analog signals into said digital data, and sequentially supplying each of said analog signals to said converting means on the basis of said scan designating value fed from said generating means.

A microcomputer comprising an analog-to-digital converting circuit and a central processing unit, said analog-to-digital converting circuit comprising:

• a plurality of input nodes respectively supplied with a plurality of analog signals;
• converting means converting each of said plurality of analog signals into digital data, and producing a finishing signal indicative of completion of such analog-to-digital conversion;
• a plurality of data registers;
• a first register temporarily storing designating data for designating one of said plurality of analog signals to be converted;
• a second register temporarily storing function mode data for designating a fixed mode or a scanning mode function;
• generating means producing scan designating data for sequentially designating analog signals selected from said plurality of analog signals;
• and
• controlling means responsive to said function mode data to allow automatic entry into said scanning mode upon termination of said fixed mode, and causing said converting means to repeat said analog-to-digital conversion on one of said analog signals into the digital data predetermined number of times for producing a predetermined number of the digital data, said controlling means further causing said converting means to sequentially convert said analog signals into a plurality of digital data after repetition of said analog-to-digital conversion, said controlling means so operating without rewriting said function mode data and having:
• first supplying means designating said one of said plurality of analog signals on the basis of said designating data stored in said first register, and supplying said one of said plurality of analog signals to said converting means until completion of said repetition;
• writing means for writing said predetermined number of said digital data converted from said one of said plurality of analog signals into data registers selected from said plurality of data registers;
• and
• second supplying means responsive to said finishing signal produced upon completion of said repetition of said analog-to-digital conversion, and sequentially supplying said analog signals to said converting means on the basis of said scan designating data fed from said generating means.

A data processor fabricated on a single semiconductor chip, comprising:

• an analog-to-digital converting unit selectively entering a fixed mode or a scanning mode of operation,
• a plurality of input nodes to which a plurality of analog input signals are respectively supplied,
• an analog-to-digital converter for converting an analog data signal to a digital data signal during an analog-to-digital converting cycle,
• a plurality of data registers coupled with said analog-to-digital converter, for writing thereinto a plurality of digital data signals sequentially supplied from said analog-to-digital converter,
• a multiplexer responsive to a selecting signal for selectively coupling said plurality of input nodes with said analog-to-digital converter, and
• a controller having
• a node-selecting register rewriteably storing a control data code indicative of one of said plurality of input nodes for producing said selecting signal indicative of said one of said plurality of input nodes in said fixed mode of operation,
• an incrementing means for producing said selecting signal for sequentially indicating said plurality of input nodes in said scanning mode,
• a mode controlling means including a function register for rewriteably storing a function code indicative of one of a first state, a second state and a third state, said fixed mode being repeated in said fist state, said scanning mode being repeated in said second state, said fixed mode being automatically followed by said scanning mode without rewriting said function code in said third state,
• a request signal producing means for producing a request signal upon completion of every write-in operation on one of said plurality of data registers in said fixed mode under said first state, upon completion of a series of write-in operations on said plurality of data registers in said scanning mode under said second state and upon completion of said fixed mode under said third state;
• and
• a central processing unit coupled with said analog-to-digital converting unit through a bus system, for supplying said control data code and said function code through said bus system to said node-selecting register and said mode controlling means when executed instruction codes request, said central processing unit being responsive to said request signal for fetching one of or said plurality of digital data signals stored in said plurality of data registers.