Phase-locked circuit capable of being quickly put in a phase-locked state

A phase-locked circuit for use in responding to a sequence of input complex sample signals to produce a sequence of output complex sample signals phase-locked with said input complex sample signals, each of said input and said output complex sample signal sequences being produced at every sample period and being carried by a complex carrier wave divisible into a real component and an imaginary component orthogonal to said real component, said phase-locked circuit comprising:

• a first complex multiplication circuit which has a pair of first input terminals, a pair of second input terminals, and a pair of output terminals and which are supplied with said input complex sample signals and a sequence of local complex sample signals through said first and said second input terminal pairs, respectively, for carrying out a first complex multiplication between said input and said local complex sample signals to produce, through said output terminal pair, first complex multiplication result signals representative of results of said first complex multiplication;
• extracting means supplied with said first complex multiplication result signals for extracting phase differences between said input and said local complex sample signals from said first complex multiplication result signals to produce complex difference signals representative of complex phase differences between said input and said local complex sample signals;
• a delay circuit supplied with said local complex sample signals for delaying said output complex sample signals by a single sample period to produce delayed complex sample signals;
• a second complex multiplication circuit supplied with said complex difference signals and said delayed complex sample signals for carrying out a second complex multiplication between said complex difference signals and said delayed complex sample signals to produce second complex multiplication result signals representative of results of said second complex multiplication;
• an output limiter supplied with said second complex multiplication result signals for limiting amplitudes of said second complex multiplication result signals to produce amplitude limited signals each of which has an invariable amplitude;
• means for producing said amplitude limited signals as said output complex sample signals;
• and
• means for supplying said output complex sample signals to said delay circuit and said first complex multiplication circuit as said local complex sample signals.