Integrated circuit device having tristate input buffer for reducing internal power use

Abstract

A large scale integrated circuit device includes a plurality of internal devices, an address decoding circuit, a bus control circuit, a first tristate buffer, and an output buffer. The internal devices are connected to an internal data bus and selectively perform data input/output operations. The address decoding circuit decodes an address signal from an address bus of a system to deliver an internal device select signal to one of the internal devices and an internal device select indication signal indicating that one of the internal devices is selected. The bus control circuit delivers an output control signal and an input control signal upon receiving the internal device select indication signal and one of a data write signal and a data read signal. The first tristate buffer controls data input to the internal data bus in accordance with the input control signal. The output buffer controls data output from the internal data bus in accordance with the output control signal.

Dependencies are inferred from the claim text.