Decoder/comparator and method of operation

A precharge device comprising:

• a first, a second and a third node;
• a plurality of decode transistors, each decode transistor comprising a first and a second current electrode and a control electrode, the first current electrode of each decode transistor coupled to the first node, the second current electrode of the decode transistor coupled to the second node, each of the control electrodes of the decode transistors coupled to one of a plurality of input signals;
• a screening transistor comprising a first and a second current electrode and a control electrode, the first current electrode coupled to the third node, the second current electrode coupled to the second node and the control electrode coupled to the first node;
• and
• clocking circuitry for precharging the first and third nodes to a first known voltage level during a first phase of a periodic clocking signal and for coupling the second node to a second known voltage level and evaluating the voltage at the first node to provide an output logic level during a second phase of the periodic clocking signal.

A comparator for comparing corresponding bits of a first and a second input, the comparator comprising:

• a first, a second and a third node;
• a plurality of pairs of circuit pathways coupled in parallel between the first and second nodes, each of the plurality of pairs of circuit pathways comprising:
• a first transistor comprising a first current electrode, a second current electrode, and a control electrode, the first current electrode coupled to the first node, the control electrode receiving an Nth bit of a first input, where N is an integer index;
• a second transistor comprising a first current electrode, a second current electrode, and a control electrode, the first current electrode coupled to the second current electrode of the first transistor, the second current electrode coupled to the second node, the control electrode receiving a logical complement of an Nth bit of a second input;
• a third transistor comprising a first current electrode, a second current electrode, and a control electrode, the first current electrode coupled to the first node, the control electrode receiving a logical complement of the Nth bit of the first input;
• a fourth transistor comprising a first current electrode, a second current electrode and a control electrode, the first current electrode coupled to the second current electrode of the third transistor, the second current electrode coupled to the second node, the control electrode receiving an Nth bit of the second input;
• a screening transistor comprising a first and a second current electrode and a control electrode, the first current electrode coupled to the third node, the second current electrode coupled to the second node and the control electrode coupled to the first node;
• and
• clocking circuitry for precharging the first and third nodes to a first known voltage level during a first phase of a periodic clocking signal and for coupling the second node to a second known voltage level and evaluating the voltage at the first node to provide an output logic level during a second phase of the periodic clocking signal.