US 5,291,070 A · Microprocessor synchronous timing system

Abstract

There is disclosed a timing system for use in a microprocessor for initiating microprocessor outputs onto an input sampling from an external bus in synchronism with a bus timing clock. The timing system is operative in a first mode for internally generating the bus timing clock and in a second mode for being driven from an externally generated bus timing clock. In the first mode, the timing system generates first and second inverse phase timing clocks responsive to an external clock source and independently generates the internally generated bus timing clock with the rising edges of the bus timing clock coinciding with the rising edges of the first microprocessor timing clock and the falling edges of the second microprocessor timing clock. In the second mode, the timing system generates the first and second microprocessor timing clocks in response to the externally generated bus timing clock. In both modes, the timing system initiates an output onto the bus upon the common assertion of the first microprocessor timing clock and the bus timing clock and initiates sampling of an input from the external bus upon the inverse assertion of the second microprocessor timing clock and the bus timing clock.

Claims42

Dependent claims

A timing system for use in a microprocessor for synchronizing the supply of output data from said microprocessor to an external bus with a bus timing clock on said external bus, said timing system comprising:

buffer means including an input for generating an intermediate clock in response to an external clock source;
first generating means coupled to said buffer means for generating first and second internal microprocessor timing clocks responsive to said intermediate clock, said first and second timing clocks being of inverse phase relation;
second generating means coupled to said buffer means for providing said external bus with said bus timing clock responsive to said intermediate clock, said second and first generating means being arranged such that the rising edges of said bus timing clock substantially coincide with the rising edges of said first timing clock and the falling edges of said second timing clock;
and
output means coupled to said first and second generating means for initiating said supply of output data from said microprocessor to said external bus upon the common assertion of said bus timing clock and said first timing clock.

2 more elements

A timing system for use in a microprocessor for providing microprocessor output data to an external bus, said timing system synchronizing said microprocessor output data with a bus timing clock, said timing system providing improved flexibility by being configured for either generating said bus timing clock responsive to an external clock source when in a first mode of operation or being driven by an externally generated bus timing clock when in a second mode of operation and comprising:

buffer means responsive to said external clock source for generating a first intermediate clock when said timing system is operable in said first mode and responsive to said externally generated bus timing clock for generating a second intermediate clock when said timing means is operable in said second mode said buffer means including an output;
first generating means coupled to said buffer means for generating first and second microprocessor timing clocks in response to said first intermediate clock when said timing system is in said first mode and in response to said second intermediate clock when said timing system is in said second mode, said first and second timing clocks being opposite in phase;
second generating means coupled to said buffer means output when said timing system is in said first mode for internally generating said bus timing clock in response to said first intermediate clock, said second generating means including an output for providing said external bus with said internally generated bus timing clock when said timing system is in said first mode, said second generating means output, when said timing system is in said second mode, receiving said externally generated bus timing clock;
enable means responsive to a select signal for coupling said second generating means to said buffer means output when said timing system is in said first mode and decoupling said second generating means from said buffer means output when said timing system is in said second mode;
and
output means coupled to said first generating means for receiving said first timing clock and coupled to said second generating means output for receiving said internally generated bus timing clock when said timing system is in said first mode or receiving said externally generated bus timing clock when said timing system is in said second mode, said output means for initiating the provision of said out data onto said external bus upon the common assertion of said first timing clock and said internally generated bus timing clock when said timing system is in said first mode or upon the common assertion of said first timing clock and said externally generated bus timing clock when said timing system is in said second mode.

3 more elements

Dependencies are inferred from the claim text.

Microprocessor synchronous timing system

Life of this patent

Microprocessor synchronous timing system

Life of this patent

Abstract

Claims42