US 5,291,065 AGranted

Semiconductor device and method of fabricating semiconductor device

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsKiyoshi Arai, Hirofumi Omachi

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Abstract

A patterned first metal plate (310)is joined to an upper surface of a first ceramic substrate (301), and a second metal plate (330) is joined to an emitter electrode (310E) of the first metal plate (310) through a second ceramic substrate (320). Power devices (4) are mounted on a collector electrode (310C) of the first metal plate (310), and control devices (5) are mounted on the second metal plate (330). The emitter electrode (310E) of a metal layer lies between a high-voltage circuit having the first metal plate (310) and power devices (4) and a control (low-voltage) circuit having the control devices (5) and second metal plate (330). The emitter electrode (310E) serves as a shielding material, and the electrostatic shielding effect prevents noises applied to the high-voltage circuit from being led to the control circuit, so that the faulty operations of the control devices (5) are prevented and the reliability of the semiconductor device is improved.

Claims20

Dependent claims

A semiconductor device comprising:

(a) a metal base plate,
(b) a composite substrate mounted on said metal base plate,
said composite substrate including:
(b-1) a first ceramic substrate joined onto said metal base plate,
(b-2) a first metal plate joined to an upper surface of said first ceramic substrate and formed into a predetermined pattern, said first metal plate having first and second regions arranged parallel to the upper surface of said first ceramic substrate,
(b-3) a second ceramic substrate joined to an upper surface of said first region of said first metal plate, and
(b-4) a second metal plate joined to an upper surface of said second ceramic substrate and formed into a predetermined pattern,
said semiconductor device further comprising:
(c) a power semiconductor device mounted on an upper surface of said second region of said first metal plate, and
(d) a control semiconductor device mounted on an upper surface of said second metal plate for controlling said power semiconductor device,
at least said second region of said first metal plate including:
(b-3-1) a first metal layer joined to the upper surface of said first ceramic substrate,
(b-3-2) a second metal layer bonded onto said first metal layer, and
(b-3-3) a third metal layer bonded onto said second metal layer,
said second metal layer being lower in coefficient of thermal expansion than said first and third metal layers,
said first region of said first metal plate being an electrode layer to be held at a constant potential.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/990,199Filed 14 Dec 1992
Priority: JP 3-33182916 Dec 1991
Granted: 1 Mar 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10W 42/20
Arrangements for protection of devices: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
H10W 42/60
Arrangements for protection of devices: protecting against electrostatic charges or discharges, e.g. Faraday shields
H10W 70/611
Insulating or insulated package substrates; Interposers; Redistribution layers: for connecting multiple chips together
H10W 90/00
Package configurations