Floating gate type electrically programmable read only memory cell with variable threshold level in erased state

An electrically programmable read only memory cell comprising

• a) source and drain regions formed in a semiconductor bulk body, and spaced apart from each other by a channel forming region,
• b) a floating gate electrode capacitively coupled with said channel forming region through a first gate insulating film,
• c) a first control gate electrode electrically isolated from said source and drain regions and said channel forming region, and capacitively coupled with said floating gate electrode through a second composite gate insulating film structure implemented by a silicon nitride film sandwiched between silicon oxide films, said first control gate electrode being biased in a write-in operation and a read-out operation, and
• d) a second control gate electrode electrically isolated from said source and drain regions, said channel forming region and said first control gate electrode, and capacitively coupled with said floating gate electrode through a third composite gate insulating film structure implemented by a silicon nitride film sandwiched between silicon oxide films, said second control ate electrode being biased when said floating gate electrode is exposed to optical radiation in an erase operation,
• wherein at least two primary grooves are formed in said semiconductor bulk body, said primary groves are lined with insulating films for forming respective secondary groves therein, and said first and second control gate electrodes are formed in said secondary grooves, respectively.

An electrically programmable read only memory device fabricated on a well formed in a single semiconductor chip, comprising:

• a plurality of memory cells each selectively entering an erased state and a write-in state for memorizing a data bit read out therefrom in a read-out operation, each of said memory cell comprising
• a) source and drain regions formed in said well and spaced apart from each other by a channel forming region,
• b) a floating gate electrode capacitively coupled with said channel forming region through a first gate insulating film,
• c) a first control gate electrode electrically isolated from said source and drain regions and said channel forming region, and capacitively coupled with said floating gate electrode through a second composite gate insulating film structure implemented by a silicon nitride film sandwiched between silicon oxide films, said first control gate electrode being biased in a write-in operation and a read-out operation, and
• d) a second control gate electrode electrically isolated from said source and drain regions, said channel forming region and said first control gate electrode, and capacitively coupled with said floating gate electrode through a third composite gate insulating film structure implemented by a silicon nitride film sandwiched between silicon oxide films, said second control gate electrode being arranged to be biased in response to exposure of said floating gate electrode to optical radiation in an erase operation that changes a threshold voltage at said first control gate electrode with respect to said channel forming region.