Non-volatile semiconductor memory device using a differential cell in a memory cell
AssigneeKabushiki Kaisha Toshiba
InventorShigeru Atsumi
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Abstract
According to this invention, in a non-volatile semiconductor memory device, each memory cell for storing 1-bit data consists of two transistors, one transistor constituting each memory cell is formed in a memory cell array consisting of a plurality of bit lines and a plurality of word lines, and the other transistor constituting each memory cell is formed in a second memory cell array consisting of a plurality of bit lines and a plurality of word lines.
Claims4
A non-volatile semiconductor memory device in which each memory cell for storing 1-bit data consists of two non-volatile transistors, comprising:
- a first memory cell array in which first transistors constituting said memory cells each having a source common pattern layout are staggered with respect to a common source region, and a second memory cell array in which second transistors constituting said memory cells are staggered with respect to a common source region;
- word lines in which every two word lines connected to said first and second memory cell arrays and sandwiching said common source region are connected to the same potential;
- first bit lines connected to said first memory cell array;
- second bit lines connected to said second memory cell array;
- bit line selecting means for selecting said first and second bit lines;
- and
- a data sense circuit for comparing signal levels of said first and second bit line selected by said bit line selecting means so as to detect data.
A device according to claim 2, wherein physical addresses of memory cells selected by the same address signal are located at identical positions of the first and second memory cells.
Dependencies are inferred from the claim text.