Method for suppressing charge loss in EEPROMs/EPROMS and instabilities in SRAM load resistors
AssigneeVLSI Technology, Inc.
InventorsVivek Jain, Dipankar Pramanik, Subhash Nariani
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Abstract
Suppression of charge loss and hot carrier degradation in EEPROMs and EPROMs, and of instability in the polysilicon pull-up resistors associated with SRAMs is achieved by the inclusion of at least one layer of silicon-enriched oxide in the MOS structure. In such MOS structures, the silicon-enriched oxide layer may be disposed immediately beneath the interlayer dielectric layer, or immediately beneath the inter-metal oxide layer, or immediately beneath the passivation layer, or in any combination of these locations. Each silicon-enriched oxide layer preferably contains at least about 10.sup.17 per cm.sup.3 dangling bonds.
Claims17
A method of making an integrated circuit MOS device having improved reliability, the method comprising:
- (a) forming on a substrate a plurality of MOS active devices, each including at least one gate;
- (b) forming a first layer of silicon-enriched oxide generally above a level of said substrate defined by said MOS active devices, said silicon-enriched oxide having a refractive index of at least 1.50 and having a layer thickness less than about 5,000 .ANG.;
- wherein said first layer of silicon-enriched oxide improves operation of said MOS devices.
Dependencies are inferred from the claim text.